Method of fabricating semiconductor device

• US 6,803,281 B2
• Filed: 02/25/2004
• Issued: 10/12/2004
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Imai, Yasuo, Ohnishi, Akihiro, Numazawa, Sumito, Kubo, Sakae
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): KESHAVAN, BELUR V
• Application Number:
  US10/785,103
• Publication Number:
  US 20040166656A1
• Time in Patent Office: 230 Days
• Field of Search: 438/270, 438/212, 438/268, 438/329, 438/328, 438/332, 438/342, 438/259, 438/272, 438/197, 438/589, 257/330, 257/327, 257/170, 257/334, 257/129, 257/341, 257/342, 257/328, 257/374, 257/397, 257/622, 257/288
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A method of manufacturing a semiconductor device having a gate lead-out region and a MISFET-forming region, comprising the steps of:

forming a trench in said MISFET-forming region of a major surface of a semiconductor substrate;

forming a gate insulating film of a MISFET in said trench;

forming a conductive film over an entire area of said major surface of said substrate such that said trench is filled by said conductive film through said gate insulating film and such that said conductive film is formed over a gate lead-out region of said major surface of said substrate; and

selectively etching said conductive film to form a gate electrode in said trench and to form a gate lead-out electrode over said gate lead-out region such that said gate lead-out electrode is integrally formed with said gate electrode,

wherein the top surface of said gate electrode is lower than the top surface of said semiconductor substrate in said gate lead-out region.

2. A method according to claim 1, wherein said conductive film is formed by a CVD method.

3. A method according to claim 1, wherein before said selectively etching step, a surface of said conductive film is flattened.

4. A method of manufacturing a semiconductor device, comprising the steps of:

forming a trench in a MISFET-forming region of a major surface of a semiconductor substrate such that said trench is not formed in a gate lead-out region of said major surface of said substrate;

forming a gate insulating film of a MISFET in said trench;

forming a conductive film over an entire major surface of said substrate such that said trench is filled by said conductive film through said gate insulating film and such that said conductive film is formed over said gate lead-out region; and

selectively etching said conductive film to form a gate electrode in said trench and to form a gate lead-out electrode over said gate lead-out region such that said gate lead-out electrode is integrally formed with said gate electrode,

wherein the top surface of said gate electrode is lower than the top surface of said semiconductor substrate in said gate lead-out region.

5. A method according to claim 4, wherein said conductive film is formed by a CVD method.

6. A method according to claim 4, wherein before said selectively etching step, a surface of said conductive film is flattened.