Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

• US 6,803,299 B2
• Filed: 04/14/2003
• Issued: 10/12/2004
• Est. Priority Date: 07/30/1997
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US10/412,317
• Publication Number:
  US 20030201477A1
• Time in Patent Office: 547 Days
• Field of Search: 257/296, 257/315, 257/324, 438/261, 438/591, 438/593, 365/185.09, 365/185.18, 365/185.24, 365/185.29
• US Class Current: 438/593
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Claims

1. A method of operating a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer, the method comprising:

programming said cell in a first direction to have a minimum width charge trapping region within said charge trapping layer; and

reading said cell with a minimum voltage on said gate in a second direction opposite to said first direction.

2. The method of claim 1, further comprising erasing said cell such that said cell does not enter deep depletion.

3. The method of claim 1, wherein said step of programming further comprises:

applying a first programming voltage to a drain of said cell;

applying a second programming voltage to said gate; and

grounding source of said cell separated from said drain by a channel, wherein said first programming voltage is substantially lower than said second programming voltage.

4. The method of claim 3, wherein the step of reading further comprises:

applying a first read voltage to said source;

applying a second read voltage to said gate;

grounding said drain; and

subsequently sensing current through said memory cell from said source to said drain.

5. The method of claim 1, wherein said step of reading further comprises:

applying a first read voltage to a source of said cell;

applying a second read voltage to said gate;

grounding a drain of said cell; and

subsequently sensing current through said memory cell from said source to said drain.

6. The method according to claim 5, wherein said read voltage applied to said gate during said step of reading said cell is not lower than the voltage sufficient to generate an inversion in said channel whereby the unprogrammed state can be sensed.

7. The method of claim 6, and wherein said read voltage applied to said gate during said step of reading said cell is limiting the voltage across a region of said channel beneath said trapped charge region to be lower than the voltage applied to said source during reading of said cell.

8. the method according to claim 5, wherein said read voltage applied to said gate during said step of reading said cell is limiting the voltage across a region of said channel beneath said trapped charge region to be lower than the voltage applied to said source during reading of said cell.