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Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

  • US 6,803,299 B2
  • Filed: 04/14/2003
  • Issued: 10/12/2004
  • Est. Priority Date: 07/30/1997
  • Status: Expired due to Term
First Claim
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1. A method of operating a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer, the method comprising:

  • programming said cell in a first direction to have a minimum width charge trapping region within said charge trapping layer; and

    reading said cell with a minimum voltage on said gate in a second direction opposite to said first direction.

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