Method for forming a semiconductor device having a mechanically robust pad interface

• US 6,803,302 B2
• Filed: 11/22/1999
• Issued: 10/12/2004
• Est. Priority Date: 11/22/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kobayashi, Thomas S., Pozder, Scott K.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MANDALA, MICHELLE
• Application Number:
  US09/443,443
• Publication Number:
  US 20010051426A1
• Time in Patent Office: 1,786 Days
• Field of Search: 438/612
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0496 : 6th Group
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134). The support structures (138) provide a mechanical barrier that protects the interface between the capping layer (204) and the bond pad (134). Additional mechanical robustness is achieved when the support structures (138) remain coupled to the unremoved portion of the dielectric layer (136), as forces buffered by the support structures (138) are distributed across the dielectric layer (136) and not concentrated at the bond pad location.

Claims

1. A method of forming a semiconductor device, comprising:

forming a first interconnect level over a semiconductor substrate;

forming an uppermost interconnect level that includes an interconnect portion and a bond pad over the first interconnect level, wherein;

the interconnect portion contacts the first interconnect level by way of vias through an interlevel dielectric layer, and wherein all vias interconnecting the interconect portion and the first interconnect level are positioned outside regions directly below the bond pad;

forming a passivation layer over the uppermost interconnect level;

removing portions of the passivation layer, wherein removing portions of the passivation layer exposes portions of the bond pad and forms a plurality of support structures overlying the uppermost surface of the bond pad; and

forming a conductive capping layer overlying the plurality of support structures, wherein the conductive capping layer electrically contacts the bond pad;

wherein the plurality of support structures are interconnected with unremoved portions of the passivation layer.

2. The method of claim 1, wherein forming the uppermost interconnect level further comprises forming the bond pad over at least one dielectric layer having a Young'"'"'s modulus less than approximately 50 Giga Pascals.

3. A method of forming a semiconductor device, comprising:

forming a first interconnect level over a semiconductor substrate;

forming an uppermost interconnect level that includes an interconnect portion and a bond pad over the first interconnect level, wherein;

the interconnect portion contacts the first interconnect level by way of vias through an interlevel dielectric layer, and wherein all vias interconnecting the interconnect portion and the first interconnect level are positioned outside regions directly below the bond pad;

forming a passivation layer over the uppermost interconnect level;

removing portions of the passivation layer, wherein removing portions of the passivation layer exposes portions of the bond pad and forms a plurality of support structures overlying the uppermost surface of the bond pad; and

forming a conductive capping layer overlying the plurality of support structures, wherein the conductive capping layer electrically contacts the bond pad;

forming a barrier layer between the capping layer and the bond pad, wherein the barrier layer overlies the support structures and abuts exposed portions of the bond pad.

4. The method o claim 3, wherein the barrier layer includes a material selected from a group consisting of tantalum, titanium, tungsten, and chromium.

9. The method of claim 3, wherein a copper content of uppermost interconnect level is at least 90 atomic percent.

10. The method of claim 3, further comprising forming dielectric studs within the bond pad, wherein at least a portion of a support structure overlies a portion of a dielectric stud.

11. The method of claim 3, wherein the dielectric layer includes a material selected from a group consisting of a nitrogen, a hydrogen, and a carbon containing silicon oxide.

12. The method of claim 3, wherein the conductive capping layer includes aluminum.

13. The method of claim 3, wherein the conductive capping layer includes a material selected from the group consisting of nickel and palladium.

5. A method of forming a semiconductor device, comprising:

depositing a dielectric layer over a semiconductor substrate;

patterning and etching a trench opening within the dielectric layer;

depositing a copper layer over the dielectric layer and within the trench opening;

removing portions of the copper layer not contained within the trench opening to define an unpermost interconnect level comprising a copper bond pad and an interconnect portion, wherein the interconnect portion physically couples to an underlying intereconnect level by way of vias, wherein the vias are positioned beyond regions directly below the copper bond pad;

forming a passivation layer over the uppermost copper bond pad;

pattering and etching the passivation layer to define openings and support structures overlying the uppermost copper bond pad;

depositing a conductive layer over the support structures and within the openings, wherein the conductive layer electrically contacts the uppermost copper bond pad;

patterning and etching the conductive layer to define a capping film over the support structures and the openings;

forming a barrier layer overlying the support structures and within the openings prior to forming the conductive layer, wherein the barrier layer electrically contacts the uppermost copper bond pad.

6. The method of claim 5, wherein the barrier layer is further characterized as a tantalum barrier layer.

7. The method of claim 6, wherein the conductive film is further characterized as an aluminum film.

8. The method of claim 5, wherein the barrier layer includes a material selected from a group consisting of titanium, chromium, tantalum nitride, titanium nitride, and chromium nitride.

14. The method of claim 5, further comprising dielectric studs disposed within the uppermost copper bond pad, wherein at least a part of a support structure overlies a dielectric stud.

15. The method of claim 5, wherein the passivation layer includes a material selected from a group consisting of nitrogen-containing silicon oxide, a hydrogen containing silicon oxide, and a carbon containing silicon oxide.

16. The method of claim 5, wherein at least one of the support structures is interconnected with unremoved portions of the passivation layer.