Power semiconductor device and production method for the same

• US 6,803,628 B1
• Filed: 09/15/2000
• Issued: 10/12/2004
• Est. Priority Date: 09/17/1999
• Status: Expired due to Fees

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Hamada, Kimimori
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): MONDT, JOHANNES P
• Application Number:
  US09/663,340
• Time in Patent Office: 1,488 Days
• Field of Search: 257/327-336, 257/341-342, 257/401, 257/491-493, 257/135, 438/212, 438/259, 438/270-1, 438/587-9
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device having a low on-resistance and a high breakdown ruggedness is disclosed. Trench regions formed so as to contact trench gates via gate-insulating films are connected by emitter regions so as to form a ladder-shaped configuration. The emitter regions are formed at a shallower depth than the trench regions. Therefore, the resistance in portions of the body that are near the interfaces with the emitter regions is reduced, and the operation of parasitic transistors formed by the emitter regions, the body, and an epitaxial layer is substantially prevented. As a result, the on-resistance is varied, and the avalanche ruggedness and the latch-up ruggedness are improved.

Claims

1. A semiconductor device comprising:

a body region of a first conductivity type formed in a semiconductor substrate and having a major surface opposite to a surface shared between the semiconductor substrate and the body region;

a plurality of trench gates extending through the body region;

a plurality of first semiconductor regions of a second conductivity type that is different from the first conductivity type, the first semiconductor regions having a first depth as measured from said major surface of the body region, at least a portion of the first semiconductor regions flanking the trench gates on both of their sides and being in contact with said trench gates via films bordering and insulating the trench gates;

a plurality of second semiconductor regions of the second conductivity type having a second depth as measured from said major surface of the body region that is less than the first depth; and

a plurality of noncontiguous third semiconductor regions of the first conductivity type whose major extension is in a direction parallel to both the major surface of the body region and the trench gates;

wherein the body region is exposed between the plurality of second semiconductor regions and the second semiconductor regions connect the plurality of first semiconductor regions spaced apart from one another.

2. A semiconductor device according to claim 1, wherein the first semiconductor regions are formed along the trench gates and the second semiconductor regions connect the first semiconductor regions formed between the trench gates so as to form a ladder-shaped configuration.

3. A semiconductor device according to claim 1, further comprising a wiring member connected to at least one of the plurality of trench gates.

4. A semiconductor device according to claim 2, further comprising a wiring member connected to at least one of the plurality of trench gates.

5. A semiconductor device according to claim 1, further comprising a wiring member connected to the body region and to the second semiconductor region.

6. A semiconductor device according to claim 2, further comprising a wiring member connected to the body region and to the second semiconductor region.