Apparatus, methods, and articles of manufacture for a switch having sharpened control voltage

• US 6,803,680 B2
• Filed: 03/18/2003
• Issued: 10/12/2004
• Est. Priority Date: 09/13/2002
• Status: Expired due to Term

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Mia-Com Incorporated
• Inventors: Kelcourse, Mark F., Brindle, Christopher N.
• Primary Examiner(s): Sircus, Brian
• Assistant Examiner(s): RIOS CUEVAS, ROBERTO JOSE
• Application Number:
  US10/390,957
• Publication Number:
  US 20040051395A1
• Time in Patent Office: 574 Days
• Field of Search: 307/115, 327/427
• US Class Current: 307/115
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

A sharp control voltage switch utilizing a plurality of field effect transistors (FETs) and a bypass resistance topology to sharpen the control voltage. Utilizing a total of six FETs allows the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

Claims

1. A switch comprising:

a plurality of field effect transistors (FETs) connected together in series; and

a bypass resistance topology, including a first terminal and a second terminal, coupled in parallel to said plurality of FETs such that the first terminal is coupled to a first of the plurality of FETs and the second terminal is coupled to a last of the plurality of FETs.

2. The switch of claim 1, wherein said bypass resistance topology is coupled between a source of the first FET of said plurality of FETs and a drain of the last FET of said plurality of FETs.

3. The switch of claim 2, wherein said bypass resistance topology includes at least one resistor coupled between the source of the first FET and the drain of the last FET.

4. The switch of claim 1, wherein said bypass resistance topology provides an alternative path for current to flow from a source voltage input to an output.

5. The switch of claim 1, further comprising at least one feed-forward capacitor coupled to at least one of said plurality of FETs.

6. The switch of claim 5, wherein said at least one feed-forward capacitor is coupled to a gate and a source of at least one of said plurality of FETs.

7. The switch of claim 5, wherein said at least one feed-forward capacitor is coupled to a gate and a drain of at least one of said plurality of FETs.

8. The switch of claim 5, wherein said at least one feed-forward capacitor includes a first feed-forward capacitor coupled to a first FET of said plurality of FETs and a second feed-forward capacitor coupled to a last FET of said plurality of FETs.

9. The switch of claim 8, wherein the first feed-forward capacitor is coupled to a source and a gate of the first FET and the second feed-forward capacitor is coupled to a drain and a gate of the last FET.

10. The switch of claim 1, wherein a first FET of said plurality of FETs is connected to a source voltage input.

11. The switch of claim 1, wherein a last FET of said plurality of FETs is connected to an output.

12. The switch of claim 1, wherein a gate of each FET of said plurality of FETs is connected to a control voltage input.

13. The switch of claim 12, further comprising a resistance coupled between at least a subset of the gates and the control voltage input.

14. The switch of claim 13, wherein said resistance includes a plurality of first resistors, at least one first resistor coupled between a gate of each of said plurality of FETs and the control voltage input.

15. The switch of claim 14, wherein each of the at least one first resistors is parallel to each other.

16. The switch of claim 14, wherein said resistance further includes a second resistor coupled between each of the at least one first resistors and the control voltage input.

17. The switch of claim 16, wherein the second resistor is coupled in series to each of the at least one first resistors.

18. The switch of claim 14, wherein said resistance further includes a plurality of second resistors, at least one second resistor coupled between each of two successive at least one first resistors and the control voltage input.

19. The switch of claim 18, wherein each of the at least one second resistors is in parallel with each other at least one second resistor and in series with each of the at least one first resistors it is coupled to.

20. The switch of claim 13, wherein said resistance includes a plurality of first resistors, at least one first resistor of the plurality of first resistors coupled between the gate of a first FET and the control voltage input and at least one second resistor of the plurality of first resistors coupled between the gate of a last FET and the control voltage input;

a plurality of second resistors coupled to the gate of each remaining FET; and

a third resistor coupled between the plurality of second resistors and the control voltage input.

21. The switch of claim 20, wherein each of the at least one second resistors is in parallel with each other, the third resistor is in series to each other of the at least one second resistors, and each of the first resistors is in parallel to each second resistor and third resistor combination.

22. The switch of claim 13, wherein said resistance includes a plurality of first resistors, at least one first resistor of said plurality of first resistors coupled between the gate of a first FET and the control voltage input, and at least one second resistor of said plurality of first resistors coupled between the gate of a last FET and the control voltage input, a plurality of second resistors coupled to the gate of each remaining FET;

and a plurality of third resistors, at least one of the plurality of third resistors coupled between two of the plurality of second resistors and the control voltage input.

23. The switch of claim 22, wherein the each of two successive second resistors is in parallel with each other, each of the at least one third resistors is in parallel with each other and is in series with the two successive second resistors it is coupled to, and each of the first resistors is in parallel to each second resistor and third resistor combination.

24. The switch of claim 1, wherein said plurality of FETs includes six gates.

25. The switch of claim 24, further comprising a first feed-forward capacitor coupled to a source and a gate of a first FET of said plurality of FETs and a second feed-forward capacitor coupled to drain and a gate of a last FET of said plurality of FETs.

26. The switch of claim 1, wherein said plurality of FETs have a single gate architecture.

27. The switch of claim 1, wherein said plurality of FETs have a multi gate architecture.

28. The switch of claim 1, wherein said plurality of FETs have a mixed gate architecture.

47. The switch of claim 1, wherein a resistance of the bypass resistance topology is less than the resistance of the plurality of FETs in an OFF state.

48. The switch of claim 47, wherein the resistance of the bypass resistance topology is greater than the resistance of the plurality of FETs in an ON state.

49. The switch of claim 1, wherein the bypass resistance topology is only coupled to the plurality of FETs at its first and second terminals.

29. A switch comprising:

a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween;

a bypass resistance topology comprising a single resistor including a first terminal and a second terminal, such that said first terminal is connected to the source of a first FET of said plurality of FETs, and said second terminal is connected to the drain of a last FET of said plurality of FETs;

a first feed-forward capacitor coupled between the source and the gate of the first FET; and

a second feed-forward capacitor coupled between the drain and the gate of the last FET.

30. The switch of claim 29, further comprising a gate resistance topology coupled between the six gates and a control voltage input.

31. The switch of claim 30, wherein said gate resistance topology includes at least one resistor coupled between each gate and the control voltage input.

32. The switch of claim 31, wherein each of the at least one resistors coupled between each gate and the control voltage input is in parallel with all other of the at least one resistors.

33. The switch of claim 31, wherein at least some portion of the at least one resistor coupled between a gate and the control voltage input includes a plurality of resistors in series with each other.

34. A device having a plurality of switches in parallel to each other and tied to same source voltage input, each switch comprising:

a plurality of field effect transistors (FETs) connected together in series, said plurality of FETs including an uppermost FET connecting to the source voltage input and a lowermost FET connecting to an output; and

a bypass resistance topology connected to the first FET and the last FET of said plurality of FETs independent of connection to any intervening FETs between the first and last FETs, said bypass resistance topology including a first terminal and a second terminal, said first terminal connected to a source of the first FET of said plurality of FETs, and said second terminal connected to a drain of the last FET of said plurality of FETs.

35. The device of claim 34, wherein each switch further comprises

a first feed-forward capacitor coupled between the source and a gate of the uppermost FET; and

a second feed-forward capacitor coupled between the drain and a gate of the lowermost FET.

36. The device of claim 34, wherein each switch further comprises a gate resistance topology coupled between gates of each FET and a control voltage input.

37. The device of claim 34, wherein each switch includes six gates.

38. A method for producing a switch having a sharpened control voltage, the method comprising:

forming a plurality of field effect transistors (FETs) connected together in series;

connecting a first FET to a source voltage source;

connecting each gate to a control voltage source;

connecting a last FET to an output; and

connecting a resistive element in parallel with the plurality of FETs, said resistive element including a first terminal and a second terminal wherein said first terminal is coupled to the first FET and said second terminal is coupled to the last FET.

39. The method of claim 38, wherein said connecting a resistive element includes connecting a resistor in parallel to all of the plurality of FETs.

40. The method of claim 38, further comprising connecting at least one feed forward capacitor to one of the plurality of FETs.

41. The method of claim 40, wherein said connecting at least one feed forward capacitor includes connecting the feed forward capacitor between a gate and either a source or a drain of the one of the plurality of FETs.

42. The method of claim 40, wherein said connecting at least one feed forward capacitor includes connecting a first feed-forward capacitor to a source and a gate of a first FET and a second feed-forward capacitor to a drain and a gate of a last FET.

43. The method of claim 38, further comprising connecting a resistance between at least a subset of the six gates and the control voltage source.

44. The method of claim 38, wherein said forming includes forming a plurality of FETs having a total of six gates.

50. The method of claim 38, wherein said connecting a resistive element comprises coupling said resistive element to the plurality of FETs by only connection of said first and second terminals to the first and last FETs, respectively.

45. A method for sharpening the control voltage of a solid state switch including a plurality of field effect transistors (FETs) connected together in series, the method comprising forming at least one resistive path in parallel with the plurality of FETs so as to provide an alternative current path from a source voltage source to an output, said at least one resistive path including a first end coupled to a first FET of the plurality of FETs, and a second end coupled to a last of the plurality of FETs.

46. The method of claim 45, wherein said forming includes forming a single resistive path in parallel with all of the plurality of FETs.

51. The method of claim 45, wherein said forming comprises coupling said at least one resistive path to the plurality of FETs by the first end coupled to the first FET and the second end coupled to the last FET independent of connection to any intervening FETs between the first and last FETs of the plurality of FETs.

52. A switch comprising:

a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween; and

a bypass resistance topology comprising a single resistor including a first terminal and a second terminal, such that said first terminal is connected to the source of a first FET of said plurality of FETs, and said second terminal is connected to the drain of a last FET of said plurality of FETs.