Input buffer circuit with constant response speed of output inversion
First Claim
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1. An input buffer circuit inverting an output corresponding to a crossing point of complementary signals, comprising:
- a first input buffer unit, including a current mirror circuit and first and second transistors connected to said current mirror circuit, comparing a voltage of an input signal input to gate terminal of said first transistor and a reference voltage input to gate terminal of said second transistor, and outputting a first output signal depending on comparison result;
a second input buffer unit, having an identical circuit configuration to said first input buffer unit, comparing a voltage of said reference voltage input to gate terminal of a third transistor corresponding to said first transistor and a voltage of a signal, complementary to said input signal, input to gate terminal of a fourth transistor corresponding to said second transistor, and outputting a second output signal depending on comparison result; and
a signal processing unit combining and buffering said first and second output signals and determining logic of said input signal.
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Abstract
Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT1, OUT2 therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT 1 and OUT 2 are combined in-phase.
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Citations
3 Claims
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1. An input buffer circuit inverting an output corresponding to a crossing point of complementary signals, comprising:
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a first input buffer unit, including a current mirror circuit and first and second transistors connected to said current mirror circuit, comparing a voltage of an input signal input to gate terminal of said first transistor and a reference voltage input to gate terminal of said second transistor, and outputting a first output signal depending on comparison result;
a second input buffer unit, having an identical circuit configuration to said first input buffer unit, comparing a voltage of said reference voltage input to gate terminal of a third transistor corresponding to said first transistor and a voltage of a signal, complementary to said input signal, input to gate terminal of a fourth transistor corresponding to said second transistor, and outputting a second output signal depending on comparison result; and
a signal processing unit combining and buffering said first and second output signals and determining logic of said input signal. - View Dependent Claims (2, 3)
an inverter element combining and buffering said first and second output signals. -
3. The input buffer circuit according to claim 1, wherein said signal processing unit further includes;
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a first inverter element buffering said first output signal, a second inverter element buffering said second output signal, and a buffer element combining output signals output from said first and second inverter elements, respectively.
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Specification
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Current AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsYasuda, Kenichi, Iga, Hironori
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Primary Examiner(s)Wambley, Patrick
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Application NumberUS10/355,167Publication NumberTime in Patent Office620 DaysField of Search326/93, 326/64, 330/255, 341/155, 327/108, 327/114, 327/333, 365/189.05, 365/74, 365/72US Class Current326/93CPC Class CodesH03K 19/00323 Delay compensation
