Integrated helix coil inductor on silicon

• US 6,803,848 B2
• Filed: 10/15/2002
• Issued: 10/12/2004
• Est. Priority Date: 03/06/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Ma, Jian Guo, Yeo, Kiat Seng, Do, Manh Anh, Chew, Kok Wai Johnny, Tan, Hai Peng
• Primary Examiner(s): Nguyen, Tuyen T
• Application Number:
  US10/271,006
• Publication Number:
  US 20030043010A1
• Time in Patent Office: 728 Days
• Field of Search: 336/65, 336/83, 336/192, 336/200, 336/206-208, 336/221, 336/225, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform. Under the fourth embodiment of the invention the height of the helix coil of the inductor of the invention is non-uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil.

Claims

1. A structure of a helix coil inductor created over a silicon substrate having a plane, comprising:

a silicon substrate having Cartesian X and Cartesian Y coordinates with corresponding silicon substrate X and Y axis perpendicularly intercepting, said point of interception of said silicon substrate X and Y axis being located in an arbitrary location over said substrate;

a multiplicity of lower level conductors located in a plane parallel with a plane of said silicon substrate, said multiplicity of lower level conductors comprising;

(i) at least one first lower level conductor having a length exceeding a length of all other lower level conductors; and

(ii) at least one second lower level conductor having a length at variance with the length of the at least one first lower level conductor;

a multiplicity of upper level conductors located in a plane parallel with said plane of said silicon substrate, whereby said upper level conductors are separated from said lower level conductors, said multiplicity of upper level conductors comprising;

(i) at least one first upper level conductor having a length exceeding a length of all other upper level conductors; and

(ii) at least one second upper level conductor having a length at variance with the length of the at least one first upper level conductor;

a multiplicity of vertical interconnect conductors of uniform height located in a plane perpendicular with said plane of said silicon substrate, said vertical interconnect conductors having a circular cross section having a radius; and

helix coil Cartesian X and Cartesian Y coordinates with corresponding helix coil X and Y axis perpendicularly intercepting.

2. The structure of claim 1, said lower level conductors comprising:

a lower level conductor width in a plane parallel with said plane of said silicon substrate;

a lower level conductor length in a plane parallel with said plane of said silicon substrate;

a lower level conductor height in a plane perpendicular to said plane of said silicon substrate;

lower level conductor lengthwise vertical sidewalls in a plane perpendicular to said plane of said silicon substrate in a direction of said lower level conductor length;

lower level conductor widthwise vertical sidewalls in a plane perpendicular to said plane of said silicon substrate in a direction of said lower level conductor width, said lower level conductor widthwise vertical sidewalls having contours of a semi-circle;

a lower level conductor upper surface in a plane parallel with said plane of said silicon substrate, said lower level conductor upper surface comprising two lower level conductor interconnect surface areas located at both extremities of length of said lower level conductor upper surface, said lower level conductor interconnect surface areas being bounded on one side by said a lower level conductor widthwise vertical sidewall;

a lower level conductor lower surface in a plane parallel with said plane of said silicon substrate; and

a lower level conductor center line located in a middle between said lower level conductor lengthwise vertical sidewalls in a direction of said lower level conductor lengthwise vertical sidewalls, furthermore being located in said lower level conductor upper surface, endpoints for said lower level conductor center line being removed from said lower level conductor widthwise vertical sidewalls by a distance being equal to said radius of said cross section of said vertical interconnect conductors.

3. The structure of claim 2, said lower level conductor interconnect surface areas being a circular surface area having a center, said center of said circular surface area of said of said lower level conductor interconnect surface areas being aligned with said endpoints of said lower level conductor center line.

4. The structure of claim 1, said upper level conductors comprising:

an upper level conductor width in a plane parallel with said plane of said silicon substrate;

an upper level conductor length in a plane parallel with said plane of said silicon substrate;

an upper level conductor height in a plane perpendicular to said plane of said silicon substrate;

upper level conductor lengthwise vertical sidewalls in a plane perpendicular to said plane of said silicon substrate in a direction of said upper level conductor length;

upper level conductor widthwise vertical sidewalls in a plane perpendicular to said plane of said silicon substrate in a direction of said upper level conductor width, said upper level conductor widthwise vertical sidewalls having contours of a semi-circle;

an upper level conductor lower surface in a plane parallel with said plane of said silicon substrate, said upper level conductor lower surface comprising two interconnect surface areas located at both extremities of length of said upper level conductor lower surface, said upper level conductor interconnect surface areas being bounded on one side by said upper level conductor widthwise vertical sidewalls;

an upper level conductor upper surface in a plane parallel with said plane of said silicon substrate; and

a upper level conductor center line being a line located in a middle between said upper level conductor lengthwise vertical sidewalls in a direction of said upper level conductor lengthwise vertical sidewalls, furthermore being located in said upper level conductor lower surface, endpoints for said upper level conductor center line being removed from said upper level conductor widthwise vertical sidewalls by a distance being equal to said radius of said cross section of said vertical interconnects.

5. The structure of claim 4, said upper level interconnect surface areas comprising a circular surface area having a center, said center of said circular surface area of said of said upper level conductor interconnect surface areas being aligned with said endpoints of said upper level conductor center.

6. The structure of claim 1, said vertical interconnect conductors comprising:

a vertical interconnect conductor height; and

a circular vertical interconnect conductor cross section.

7. The structure of claim 1, comprising:

a helix coil length in a plane parallel with said plane of said surface of said silicon substrate measured in a direction of said helix coil X Cartesian coordinate;

a helix coil width in a plane parallel with said plane of said silicon substrate measured in a direction of said helix coil Y Cartesian coordinate, said helix coil length and said helix coil width being aligned with said helix coil Cartesian X and Cartesian Y coordinates, with corresponding helix coil X axis and Y axis perpendicularly intercepting, whereby said point of interception of said helix coil X and Y axis is located in an arbitrary position over said substrate; and

a helix coil height in a plane perpendicular to said plane of said silicon substrate.

8. The structure of claim 1, said substrate point of Cartesian intercept being aligned with said helix coil point of Cartesian, said helix coil point of Cartesian intercept being selected over said substrate as a location where said helix coil inductor is created, thereby implying a fixed orientation of said helix coil Cartesian X axis and Cartesian Y axis.

9. The structure of claim 1, said upper level conductors comprising:

a maximum length upper level conductor created in equal lengths in a direction of said Y and the Y′

axis of said helix coil Cartesian coordinates having an upper level conductor length being longer than all other conductors within said multiplicity of upper level conductors; and

a multiplicity of upper level conductors created parallel with said maximum length upper level conductor, located on both sides of said maximum length upper level conductor, a length of said multiplicity of upper level conductors being created in equal lengths in the Y and the Y′

direction of said helix coil Cartesian coordinates, whereby furthermore the length of said multiplicity of upper level conductors uniformly decreases with increasing distance between said maximum length upper level conductor and said multiplicity of upper level conductors.

10. The structure of claim 9, centers of upper level conductor interconnect surface areas on a lower surface of said maximum length upper level conductor being located on said Y-Y′

axis of said helix coil Cartesian coordinates and at equal distances from said intersect of said helix coil Cartesian coordinates at points +Y max upper and −

Y max upper.

11. The structure of claim 1, said lower level conductors comprising:

a maximum length first and a second lower level conductor, extending in equal lengths from points of intercept of a lower level conductor upper surface lengthwise center line with said X-X′

axis of said helix coil Cartesian coordinates, said points of intercept being located equidistant from a point of intercept of the X-X′ and

Y-Y′

axis of said helix coil Cartesian coordinates, a lengthwise center line of said lower level conductor upper surfaces intersecting under an angle with the Y-Y′

direction of said helix coil Cartesian coordinates, furthermore said maximum length first and second lower level conductor having a lower level conductor lengths being longer than all other lower level conductors within said multiplicity of lower level conductors, whereby furthermore a center of said lower level conductor interconnect surface area of said first maximum length lower level conductor is aligned with said point +Y max upper, a center of said interconnect surface areas of said second maximum length lower level conductor being aligned with said point −

Y max upper; and

a multiplicity of conductors created parallel with said maximum length first and second lower level conductors located in essentially equal numbers on both sides of said maximum length lower level conductors extending in equal lengths from a point of intercept of said centers of said lower surfaces of said lower level conductors with said X-X′

axis of said helix coil Cartesian coordinates, furthermore the length of said multiplicity of lower level conductors uniformly decreasing with increasing distance between said maximum length first and second lower level conductors and said multiplicity of conductors.

12. The structure of claim 1, said upper level conductors and said lower level conductors being joined by said vertical interconnects, comprising:

a first and second vertical interconnect provided to said maximum length upper level conductor overlying an upper level conductor interconnect surface area of a lower surface of said maximum length upper level conductor, said first and second vertical interconnects facing towards lower level conductors, centers of said first and second vertical interconnects being aligned with centers of said interconnect surface areas of said lower surface of said maximum length upper level conductor; and

a multiplicity of vertical interconnects provided between corresponding interconnect surface areas on the lower surface of said upper level conductors and on the upper surface of said lower level conductors.

13. The structure of claim 1 whereby said structure is embedded in a dielectric and furthermore covered by a layer of passivation.

14. The structure of claim 11, said maximum length upper level conductor and said maximum length lower level conductor not being restricted to one upper level conductor and two lower level conductors, extending to a multiplicity of upper level and lower level conductors with a centrally located conductor of said multiplicity of conductors assuming a structural function equivalent to a structural function of said single maximum length upper level conductor and said two maximum length lower level conductors.

15. The structure of claim 1L whereby additionally input and output connections are provided to said structure by providing interconnects to two upper level or lower level conductors of said structure being of shortest length when compared to all other upper level or lower level conductors of said helix coil.

16. A structure of a helix shaped inductor on a silicon substrate, comprising:

a silicon substrate;

lower level conductors over said silicon substrate in a plane parallel with a plane of said substrate;

upper level conductors over said silicon substrate in a plane parallel with a plane of said substrate;

interconnects over said silicon substrate having a height in a plane perpendicular to a plane of said substrate, said interconnects connecting said lower level conductors to said upper level conductors, thereby leaving a space between said upper and lower level conductors;

an axis, said axis being parallel with said substrate;

a length;

a width, said width changing in the direction of said axis from a maximum width at a center of said axis to smaller values of width when proceeding from said center of said axis in either direction of said center; and

a height.

17. The structure of claim 16 whereby said height of said interconnects is constant.