Read-modify-write memory using read-or-write banks
First Claim
Patent Images
1. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
- a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and
wherein the read-modify-write bank has a cycle time that is smaller than the sum of the read cycle time and write cycle time of a slowest read-or-write bank in the memory arrangement, wherein the circuit arrangement is adapted to effect a read-modify-write cycle time that is smaller than the sum of the slowest read-or-write bank'"'"'s read cycle time and write cycle time.
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Accused Products
Abstract
Minimal memory access times are realized by using a single access to a read-modify-write bank. A read-modify-write memory including at least one read-or-write bank is operated in a manner that uses at most one access to each of the at least one read-or-write banks for each read-modify-write access to the memory during a memory cycle. The access can be effected during a single clock cycle and can be used for read, write and read-modify-write memory access.
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Citations
57 Claims
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1. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and
wherein the read-modify-write bank has a cycle time that is smaller than the sum of the read cycle time and write cycle time of a slowest read-or-write bank in the memory arrangement, wherein the circuit arrangement is adapted to effect a read-modify-write cycle time that is smaller than the sum of the slowest read-or-write bank'"'"'s read cycle time and write cycle time.
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2. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and
wherein the at least one read-or-write bank includes a plurality of read-or-write banks and wherein the read-modify-write bank is adapted to be used as a cache for the plurality of read-or-write banks.
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3. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and
wherein the storage capacity of the read-modify-write bank is at least the storage capacity of the largest read-or-write bank.
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4. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank;
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
at least one pipeline register adapted to store data;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and
wherein the storage capacity of the read-modify-write bank is at least the storage capacity of a largest one of the read-or-write banks less the storage capacity of the pipeline registers.
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5. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify -write access to the memory; and
wherein memory addresses in the circuit arrangement are partitioned into a bank address that identifies a particular read-or-write bank and a row address that identifies a particular word within the read-or-write bank.
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6. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle and adapted to provide control signals for effecting the at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory;
wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory.
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7. A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:
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a memory having at least one read-or-write bank electrically coupled to a read-modify-write bank having a tag that indicates a read-or-write bank to which data in the read-modify-write bank belongs; and
control circuitry adapted for using at most one access to each said at least one read-or-write bank and one access to the read-modify-write bank, for each read-modify-write access to the memory during a single memory access cycle. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including using a control circuit adapted to effect the read-modify-write access using at most one access to each said at least one read-or-write bank. - View Dependent Claims (17, 18)
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19. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including using at least one read-modify-write cache. - View Dependent Claims (20)
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21. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including reading a word from a read-or-write bank that is adapted for destructive reading and writing the unmodified read word back into the read-or-write bank that it was read from.
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22. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including error-correction of encoded words with partial word writes, the method further comprising;
reading an encoded word from the at least one read-or-write bank;
decoding the encoded word;
modifying the decoded word by inserting a partial word;
re-encoding the modified decoded word; and
writing the re-encoded word into the at least one read-or-write bank.
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23. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including overlapping a read-modify-write cache access with the read-or-write bank access such that the read-modify-write cycle time is smaller than the sum of the slowest read-or-write bank'"'"'s read cycle time and write cycle time. - View Dependent Claims (24)
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25. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle, including performing a late select that includes simultaneously effecting a read of the addressed read-or-write bank and a read of a tag that indicates which read-or-write bank'"'"'s data is in a cache, wherein data from the read-or-write bank is returned in response to the tag indicating that the data in the cache does not correspond to the addressed read-or-write bank and wherein data from the cache is returned in response to the tag indicating that the data in the cache corresponds the addressed read-or-write bank.
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26. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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receiving an incoming address request;
reading a word from a row of a read-or-write bank corresponding to the incoming address;
reading a word from a row of a cache corresponding to the row of the read-or-write bank;
reading a tag of the cache that indicates which read-or-write bank'"'"'s word is contained in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, returning data from the cache for the read access; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, returning data from the read-or-write bank for the read access. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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receiving an incoming address request for a write access to the memory;
reading a tag of a cache having a word for one of the at least one read-or-write banks stored therein, the tag indicating which read-or-write bank'"'"'s word is stored in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address request, writing data to the cache for the write access; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address request, writing data to the read-or-write bank for the write access. - View Dependent Claims (40)
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41. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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receiving an incoming address request for a write access to the memory;
reading a tag of a cache having a word for one of the at least one read-or-write banks stored therein, the tag indicating which read-or-write bank'"'"'s word is stored in the cache; and
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address request, writing data to the read-or-write bank corresponding to the incoming address request for the write access and invalidating the data in the cache.
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42. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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receiving an incoming address request for a write access to the memory;
reading a tag of a cache having a word for one of the at least one read-or-write banks stored therein, the tag indicating which read-or-write bank'"'"'s word is stored in the cache; and
in response to the tag indicating that the cache does not contain the word of the read-or-write bank corresponding to the incoming address request, writing data from the cache to the read-or-write bank corresponding to the cache tag. - View Dependent Claims (43, 44, 45, 46, 47)
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48. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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receiving an incoming address request;
reading a word from a row of a cache corresponding to the row of the read-or-write bank at the incoming address;
reading a tag of the cache that indicates which read-or-write bank'"'"'s word is stored in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, modifying the word read from the cache and writing the modified word back to the cache; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, writing the word read from the cache to the read-or-write bank corresponding to the tag, reading a word from the row of the read-or-write bank corresponding to the incoming address, modifying the word read from the read-or-write bank corresponding to the incoming address, writing the modified word to the cache and updating the tag to indicate that the word in the cache contains the word from the read-or-write bank corresponding to the incoming address. - View Dependent Claims (49)
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50. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
using at least one pipeline register to store data, including separating a cache read from a read-or-write bank write.
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51. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
using at least one pipeline register to store data, including using pipeline forwarding. - View Dependent Claims (52)
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53. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
writing a partial word to at least one of the said at least one read-or-write bank;
wherein writing a partial word comprises;
reading a word from a read-or-write bank;
replacing a portion of the read word with the partial word; and
writing the work having the partial word back to the read-or-write bank.
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54. The A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
writing a partial word to at least one of the said at least one read-or-write bank;
wherein writing the partial word includes spatially separating memory cells accessed by the partial word from other memory cells in the word.
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55. A method for providing read-modify-write memory from a memory having at least one read-or-write bank, the method comprising:
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using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; and
writing a partial word to at least one of the said at least one read-or-write bank;
wherein writing the partial word includes constructing logical memory out of a plurality of actual memories including the at least one read-or-write bank and writing a partial word to the actual memories.
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56. A method for providing read-modify-write memory from a memory having at least one read-or-write bank wherein at most one access to each said at least one read-or-write bank is generated for each read-modify-write access to the memory, the method comprising:
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in response to receiving a read access request for an incoming address;
reading a word from a row of a read-or-write bank corresponding to the incoming address;
reading a word from a row of a cache corresponding to the row of the read-or-write bank;
reading a tag of the cache that indicates which read-or-write bank'"'"'s word is contained in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, returning data from the cache for the read access; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, returning data from the read-or-write bank for the read access;
in response to receiving a write access request for an incoming address;
reading a tag of the cache that indicates which read-or-write bank'"'"'s word is contained in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address request, writing data to the cache for the write access; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address request, writing data to the read-or-write bank for the write access; and
in response to receiving a read-modify-write access request for an incoming address;
reading a word from a row of a cache corresponding to the row of the read-or-write bank;
reading a tag of the cache that indicates which read-or-write bank'"'"'s word is contained in the cache;
in response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, modifying the word read from the cache and writing the modified word back to the cache; and
in response to the tag not indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, writing the word read from the cache to the read-or-write bank corresponding to the tag, reading a word from a row of a read-or-write bank corresponding to the incoming address, modifying the word read from the read-or-write bank corresponding to the incoming address, writing the modified word to the cache and updating the tag to indicate that the word in the cache contains the word from the read-or-write bank corresponding to the incoming address. - View Dependent Claims (57)
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Specification