Broadband I/O circuits, interface and bus

• US 6,804,292 B2
• Filed: 11/13/2001
• Issued: 10/12/2004
• Est. Priority Date: 02/22/1999
• Status: Expired due to Term

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: PCTEL, Inc.
• Inventors: Liu, Ming-Kang, Young, Whu-ming
• Primary Examiner(s): Fan, Chieh M.
• Application Number:
  US10/054,294
• Publication Number:
  US 20020064222A1
• Time in Patent Office: 1,064 Days
• Field of Search: 375/219, 375/220, 375/222, 375/257, 375/260, 375/296, 375/346, 370/294, 370/468, 370/485, 370/498, 370/501, 710/1, 710/305
• US Class Current: 375/222
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data

Abstract

A broadband digital communications link, protocol and related I/O circuits are provided which use an embedded control channel and a frame structure for transferring control information between different sections of a broadband system, including within a personal computer. A dedicated bus within the personal computer is used to support a variety of devices using the broadband link, and clocking is performed with a combination of bit clocks and frame clocks that are adjustable to accommodate needs of disparate types of data, including data for an xDSL communications path, xDSL samples from different analog codecs for xDSL modems, and ATM cells for an ATM interfaces. The I/O circuits include multiple bus interfaces to make them more flexibly integrated into a variety of application environments.

Claims

1. A method of implementing a digital communications link connecting a digital controller section of a broadband signal modem, located on a system motherboard of a computing system, to a separate analog section of the broadband signal modem, located at a position which is substantially free of electronic noise from other electronic components on said motherboard which could significantly affect the overall operation of such broadband signal modem, said method comprising the steps of:

(a) providing a plurality of receive signal lines for communicating data from a remote broadband signal modem;

(b) providing a plurality of transmit signal lines for communicating data to the remote broadband signal modem;

(c) providing a bit clock signal line separate from said plurality of receive signal lines and said plurality of transmit signal lines for carrying a bit clock signal, which bit clock signal is used in connection with communicating said data to and from said remote broadband signal modem;

(d) providing a frame signal to mark the boundary for a data frame received and/or transmitted on said plurality of receive signal lines and said plurality of transmit signal lines.

2. The method of claim 1, further including a step (e):

providing a reset signal to reset the analog section of the broadband signal modem.

3. The method of claim 1, wherein at least four (4) signal lines are used for said receive signal lines, and at least (4) separate signal lines are used for said transmit signal lines.

4. The method of claim 1, wherein the frame signal is based on a word clock that has a word clock cycle consisting of at least four (4) bit clock cycles, with a first bit clock cycle being a first value and the remaining bit clock cycles being a second value.

5. The method of claim 1, wherein said receive and/or transmit signal lines can also be used for implementing an embedded operation channel within said receive and/or transmit signal lines, said embedded operation channel consisting of control signals embedded in both transmit and receive directions for use by the broadband signal modem.

6. The method of claim 4, wherein at least one (1) bit per word clock cycle is used to carry control signals.

7. The method of claim 5, wherein each control signal can have either a first or second length.

8. The method of claim 5, wherein each control signal begins with a start bit, is followed by a length bit, then by a set of command bits, and then idle bits are sent between control signals.

9. The method of claim 1, further including a step:

providing a multi-channel data frame, said multi-channel data frame having at least two data channels, and wherein data is transferred through a first channel during a first time period of said multi-channel data frame, and through a second channel during a second time period of said multi-channel data frame.

10. The method of claim 9, wherein the number of channels in the multi-channel data frame is programmable.

11. The method of claim 9, wherein a word clock signal used for clocking data words for said data frame consists of at least four (4) bit clock cycles, and such that data for a single data frame is clocked in parallel across all of said receive and/or said transmit signal lines during data communications.

12. The method of claim 11, wherein said word clock signal is used to mark the boundary of each multi-channel data frame by having a predetermined value for two bit clock cycles at the frame beginning and said word clock signal has said predetermined value for only one bit clock cycle for each word beginning in the rest of the frame.

13. The method of claim 1, wherein said receive and/or said transmit signal lines can also be used to support a data interface between said digital controller and a hardware or DSP based broadband signal modem.

14. The method of claim 13, wherein the data interface is logically equivalent to a Utopia I and/or II interface and said hardware or DSP based broadband signal modem also can perform an ATM transport convergence (TC) function.

16. The method of claim 1, wherein said bit clock signal is based an external master clock operated at a frequency required by the broadband signal modem.

15. The method of 14, wherein an embedded operation channel (EOC) is used to control proper operations of the hardware or DSP based broadband signal modem.

17. A communications protocol for transmitting data on a broadband digital communications link between a digital controller and an analog codec located within a personal computer system, said protocol comprising the steps of:

(a) generating a bit clock signal and a separate frame signal adapted for data transmission requirements of the broadband digital communications link;

(b) communicating data frames using said frame signal between the digital controller and analog codec at a rate based on said bit clock;

(c) communicating operational and/or control information for the broadband digital communications link between the digital controller and analog codec by embedding said operational and/or control information within said data frames;

wherein both operational and/or control information and data can be exchanged between the digital controller and the analog codec within a single data frame;

wherein said operational and/or control information includes information relating to real time control settings for circuits located within the analog codec.

18. The protocol of claim 17, wherein said operational and/or control information further includes information relating to power management for an xDSL modem.

19. The protocol of claim 18, where in said operational and/or control information consists of control data words that are transmitted asynchronously with respect to data words.

20. The protocol of claim 19, wherein a start bit is used within said operational and/or control information to indicate the beginning of a valid control data word.

21. The protocol of claim 19, wherein said control data words are communicated over a single set of data lines.

22. The protocol of claim 21, further wherein multiple data channels are operated between the digital controller and analog codec on said single set of data lines.

23. The protocol of claim 22, wherein said frame signal has a first duration for data communications in said first data channel, and a second duration for data communications in said second data channel.

24. The protocol of claim 17, wherein the protocol is used on a system motherboard of a computing system such that the digital controller is located on said system motherboard and the analog codec is located at a position which is substantially free of electronic noise from other electronic components on said system motherboard which could significantly affect the overall operation of such broadband digital communications link.

25. A communications protocol for transmitting data on a broadband digital communications link between a digital controller and an analog codec located within a personal computer system, said protocol comprising the steps of:

(a) generating a bit clock signal and a separate frame signal adapted for data transmission requirements of the broadband digital communications link;

(b) communicating data frames using said frame signal between the digital controller and analog codec at a rate based on said bit clock;

(c) communicating operational and/or control information for the broadband digital communications link between the digital controller and analog codec by embedding said operational and/or control information within said data frames;

(d) transmitting embedded control information from the digital controller to the analog codec indicating loss of power in the personal computer system;

wherein both operational and/or control information and data can be exchanged between the digital controller and the analog codec within a single data frame.

26. A digital controller for use with a broadband modem comprising:

a) means for processing data from the broadband modem and received control signals; and

b) means for generating transmit control signals associated with supporting a broadband protocol used by the broadband modem; and

c) a digital interface for coupling the digital controller to an analog CODEC associated with the broadband modem, said digital interface including;

[i] a plurality of receiving lines for receiving broadband data; and

[ii] a plurality of transmitting lines for transmitting broadband data; and

[iii] a bit clock signal adapted for said broadband protocol; and

[iv] a frame signal for clocking a variable sized data frame; and

wherein said digital controller is adapted to be physically placed on a computer motherboard, and wherein both said transmit control signals and said broadband data are transmitted within a single data frame.

27. The digital controller of claim 26, wherein said transmit control signals and said received control signals are asynchronously transmitted with respect to said broadband data.

28. The digital controller of claim 26, wherein said digital interface can handle a multi-channel data frame, said multi-channel data frame having at least two data channels, and wherein data for a first channel can be transferred during a first time period of said multi-channel data frame, and data for a second channel can be transferred during a second time period of said multi-channel data frame.

29. The digital controller of claim 26, wherein said transmit control signals relate to real time control settings for circuits located within the analog codec.

30. The digital controller of claim 26, wherein said transmit control signals relate to power management for the broadband modem.

31. An analog codec for use with a broadband modem comprising:

a) line interface circuitry for coupling to a data channel carrying analog data signals corresponding to data for the broadband modem; and

b) circuitry for performing A/D and D/A operations on said analog data signals and formatted data respectively; and

c) a digital interface for interfacing to a digital controller located on a computer motherboard, said digital interface being coupled to a plurality of broadband data receiving lines and a plurality of broadband data transmitting lines, said digital interface being further configured such that;

[i] broadband data signals are received using said plurality of broadband data receiving lines; and

[ii] broadband data signals are transmitted using said plurality of broadband data transmitting lines; and

[iii] a bit clock signal adapted for requirements of a broadband data link can be used by the digital interface; and

[iv] a frame signal can be used for clocking a variable sized broadband data frame; and

wherein the analog codec is adapted to be physically separated from said digital controller.

32. The codec of claim 31, wherein said variable sized broadband data frame also includes control information that is separate from said formatted data.

33. The codec of claim 31, wherein said digital interface can handle a multi-channel variable sized broadband data frame, said multi-channel variable sized broadband data frame having at least two data channels, and wherein data can be transferred through a first channel during a first time period of said multi-channel variable sized broadband data frame, and through a second channel during a second time period of said multi-channel variable sized broadband data frame.

34. The codec of claim 32, wherein said control information relates to real time control settings for circuits located within the analog codec and/or analog front circuitry associated with the broadband modem.

35. The codec of claim 32, wherein said control information relates to power management operations to be performed by the broadband modem.

36. In a motherboard for use in a personal computing system, and which system is configured to support a high speed broadband modem, the improvement comprising:

(A) a digital controller associated with the high speed modem, said digital controller being located physically on the motherboard and including;

[ii] circuitry for processing data and control signals formatted for the high speed broadband modem; and

(B) an analog front end circuit associated with the high speed broadband modem, said analog front end circuit being electrically coupled but physically separated from said digital controller, said analog front end circuit including;

[i] line interface circuitry for coupling to a data channel carrying analog data signals corresponding to said data and control signals formatted for the high speed broadband modem; and

[ii] circuitry for performing A/D and D/A operations on said analog data signals and data and control signals formatted for the high speed broadband modem respectively; and

(C) a digital interface for coupling said digital controller and analog front end circuit, said digital interface including;

[i] a plurality of data receiving lines; and

[ii] a plurality of data transmitting lines; and

[iii] a clock signal adapted to support a broadband data link clock rate; and

wherein said digital interface time division multiplexes data and control signals to support said broadband data link between said digital controller and said analog front end circuit.

37. The motherboard of claim 36, wherein said analog front end circuit is located on a riser card which is configured to be mounted substantially perpendicular to the motherboard.

38. The motherboard of claim 36, wherein said digital controller is controlled in part in software by a host processor located on the motherboard.

39. The motherboard of claim 36, further wherein said digital interface uses a multi-channel data frame, said multi-channel data frame having at least two data channels, and wherein data for a first channel is transferred during a first time period of said multi-channel data frame, and data for a second channel is transferred during a second time period of said multi-channel data frame.

40. The motherboard of claim 36, wherein said receive and/or transmit signal lines can also be used to transport asynchronous mode transfer (ATM) cells.

41. The motherboard of claim 36, wherein said digital interface is also coupled to an ATM interface that is a Utopia I and/or II interface.

42. An input/output (I/O) circuit adapted for use with a digital subscriber loop (xDSL) communication link in a personal computer system, the I/O circuit comprising:

(a) a universal serial bus (USB) interface; and

(b) a peripheral component interconnect (PCI) interface; and

(c) an audio-code (AC)-97 interface; and

(d) an xDSL bus interface, including;

i) an xDSL data buffer for storing xDSL data associated with an xDSL data transmission in the xDSL communication link;

ii) a digital interface for transferring said xDSL data between a digital controller and at least one analog CODEC associated with the xDSL communication link, said digital interface including;

1) a plurality of receiving lines for receiving xDSL data; and

2) a plurality of transmitting lines for transmitting xDSL data; and

3) a bit clock signal line for carrying a bit clock signal adapted for an xDSL protocol used by the xDSL communication link;

4) a frame clock signal line for carrying a frame clock signal adapted for clocking a variable sized data frame over the xDSL communications link.

43. The I/O circuit of claim 42 wherein said variable sized data frame is adapted to transport xDSL data in the form of:

(a) digital data samples for an xDSL software modem;

(b) asynchronous transfer mode (ATM) cell data for a hardware and/or DSP based xDSL modem.

44. The I/O circuit of claim 42 wherein said digital controller and I/O circuit are incorporated within a single integrated circuit, and said digital controller performs at least some signal processing operations required for the xDSL data.

45. The I/O circuit of claim 42 wherein said variable sized data frame is programmable by a host computer system to accommodate one or more xDSL modems.

46. The I/O circuit of claim 42 wherein said variable sized data frame is varied according to a number of data channels required over the xDSL communications link.

47. The I/O circuit of claim 42 wherein said I/O circuit is mounted on a computer motherboard and coupled to a computer bus used to support said xDSL communication link.

48. An input/output (I/O) circuit for implementing a bus protocol supporting a plurality of separate data communication channels over a computer bus used within a personal computer system, the I/O circuit including:

a digital communications interface including;

1) a plurality of receive lines for receiving data from each of the plurality of separate data channels in accordance with the bus protocol; and

2) a plurality of transmit lines, separate from said plurality of receive lines, for transmitting data to each of the plurality of separate data channels in accordance with the bus protocol;

wherein the plurality of separate data channels transmit data in parallel across said plurality of receive lines and said plurality of transmit lines in accordance with the bus protocol;

3) a bit clock signal line, separate from said plurality of receive lines and said plurality of transmit lines, for carrying a bit clock signal adapted for a transmission protocol supported by the bus protocol;

4) a frame signal line for carrying a frame clock signal adapted for clocking a variable sized data frame in accordance with the bus protocol, said variable sized data frame having a size based on a number of active channels in the plurality of separate data channels and/or a desired data rate;

wherein said plurality of receive lines, said plurality of transmit lines, said bit clock signal line and said frame clock signal line support the bus protocol as part of the communications bus within the personal computer system.

49. The I/O circuit of claim 48 further including:

(a) a universal serial bus (USB) interface;

(b) a peripheral component interconnect (PCI) interface; and

(c) an audio-code (AC)-97 interface.

50. The I/O circuit of claim 48 wherein said frame clock signal line carries a word clock signal, and said frame signal is formed from a plurality of word clock signals.

51. The I/O circuit of claim 50, wherein said word clock signal is used to mark the boundary of said variable sized data frame by having a predetermined value for a first number of bit clock cycles at the frame beginning to form said frame signal, and said word clock signal has said predetermined value for a second number of bit clock cycles for each word beginning in the rest of the variable sized data frame.

52. The I/O circuit of claim 48, wherein operational and/or control information for each of a plurality of separate CODECs is embedded in data words communicated through a respective plurality of data channels.

53. The I/O circuit of claim 48, wherein the I/O circuit includes a digital controller located on a system motherboard of the personal computing system, and a plurality of analog codecs are located at positions which are substantially free of electronic noise from other electronic components on said system motherboard which could materially affect the operation of such plurality of analog codecs.

54. An input/output (I/O) circuit adapted for use with a digital subscriber loop (xDSL) communication link in a personal computer system, the I/O circuit comprising:

(a) a universal serial bus (USB) interface; and

(b) a peripheral component interconnect (PCI) interface; and

(c) an audio-code (AC)-97 interface; and

(d) an xDSL bus interface, including;

i) an xDSL data buffer for storing xDSL data associated with an xDSL data transmission in the xDSL communication link;

ii) a digital interface for transferring said xDSL data between a digital controller and at least one analog CODEC associated with the xDSL communication link, said digital interface including;

1) a plurality of receiving lines for receiving xDSL data; and

2) a plurality of transmitting lines for transmitting xDSL data; and

3) a bit clock signal line for carrying a bit clock signal adapted for an data transmission protocol used by the xDSL communication link, said bit clock signal line being separate from said plurality of receiving lines and said plurality of transmitting lines;

wherein said xDSL data can be in the form of;

(a) digital data samples for a first type of xDSL modem implemented in part by software operating on a host processor of the personal computer system; and

/or (b) asynchronous transfer mode (ATM) data including ATM cells for a second type of xDSL modem implemented in hardware and/or in a DSP.

55. The I/O circuit of claim 54 wherein said digital controller and I/O circuit are incorporated within a single integrated circuit, and said digital controller performs at least some signal processing operations required for the xDSL data.

56. The I/O circuit of claim 54 wherein said I/O circuit is mounted on a computer motherboard and coupled to a computer bus used to support said xDSL communication link.

57. The I/O circuit of claim 54 wherein said digital data samples are output from an A/D converter from an analog front end circuit associated with said xDSL modem, such that for any sample word a most significant bit is transmitted first, and a least significant bit is transmitted last.

58. The I/O circuit of claim 54 wherein the I/O circuit supports an ATM interface when said ATM data are transferred over the xDSL communications link such that:

(a) during a first cycle of bit clock signal periods, ATM control data is transmitted in parallel over said plurality of receiving lines and/or plurality of transmitting lines; and

(b) during a second cycle of bit clock signal periods, ATM control data and ATM address data is transmitted in parallel over said plurality of receiving lines and/or plurality of transmitting lines; and

(c) during a third cycle of bit clock signal periods, most significant bits of data for an ATM cell are transmitted in parallel over said plurality of receiving lines and/or plurality of transmitting lines; and

(d) during a fourth cycle of bit clock signal periods, least significant bits of data for said ATM cell are transmitted in parallel over said plurality of receiving lines and/or plurality of transmitting lines.