System for coordination of TDD transmission bursts within and between cells in a wireless access system and method of operation

• US 6,804,527 B2
• Filed: 04/20/2001
• Issued: 10/12/2004
• Est. Priority Date: 01/19/2001
• Status: Expired due to Term

• Current Assignee: Access Solutions, Ltd. (LOXAM SAS)
• Original Assignee: Raze Technologies, Inc.
• Inventors: Struhsaker, Paul F., Griffin, Kirk J., Eckert, Michael S.
• Primary Examiner(s): Trost, William
• Assistant Examiner(s): Ferguson, Keith
• Application Number:
  US09/839,512
• Publication Number:
  US 20020137533A1
• Time in Patent Office: 1,271 Days
• Field of Search: 455/502, 455/503, 455/550, 455/561, 455/517, 455/500, 455/524, 455/525, 455/555, 455/554, 455/403, 455/422, 455/426, 370/503, 370/508, 370/509, 370/510, 370/512, 370/350, 370/347, 370/362, 370/321
• US Class Current: 455/502
• CPC Class Codes: H01Q 1/246 specially adapted for base stations
• CPC Class Codes: H04J 3/0694 Synchronisation in a TDMA node, e.g. TTP
• CPC Class Codes: H04L 1/0005 applied to payload information
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0017 where the mode-switching is based on Quality of Service requirement
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2001/0098 Unequal error protection
• CPC Class Codes: H04M 2207/206 composed of PSTN and wireless network
• CPC Class Codes: H04M 2242/04 for emergency applications
• CPC Class Codes: H04M 2242/06 Lines and connections with preferential service
• CPC Class Codes: H04M 3/42 Systems providing special services or facilities to subscribers specially adapted for wireless communication networks H04W4/00
• CPC Class Codes: H04W 28/18 Negotiating wireless communication parameters
• CPC Class Codes: H04W 56/0015 one node acting as a reference for the others
• CPC Class Codes: H04W 84/14 WLL [Wireless Local Loop]; RLL [Radio Local Loop]
• CPC Class Codes: H04W 88/021 adapted for Wireless Local Loop operation
• CPC Class Codes: H04W 88/08 Access point devices

Abstract

There is disclosed, for use in a first radio frequency (RF) modem shelf associated with a first one of a plurality of base stations in a fixed wireless access network, a timing distribution apparatus for synchronizing the operations of a plurality of RF modems in the first RF modem shelf. The timing distribution apparatus comprises: a) a primary master clock source for generating an internal master clock signal and an internal master framing signal; b) a plurality of interface control processors capable of synchronizing a downlink transmission of one of the plurality of RF modems; c) a synchronization bus; d) an external interface input port capable of receiving an external master synchronization signal from a second RE modem shelf; and e) an external interface output port for transmitting at least one of the internal master clock signal and the internal master framing signal to the second RF modem shelf.

Claims

1. For use in a first radio frequency (RF) modem shelf associated with a first one of a plurality of base stations in a fixed wireless access network, a timing distribution apparatus for synchronizing the operations of a plurality of RF modems in said first RF modem shelf comprising:

a primary master clock source capable of generating an internal master clock signal and an internal master framing signal;

a plurality of interface control processors, each of said interface control processors capable of receiving said internal master clock signal and said internal master framing signal and capable of using said internal master clock signal and said internal master framing signal to synchronize a downlink transmission of one of said plurality of RF modems;

a synchronization bus capable of distributing said internal master clock signal and said internal master framing signal from said primary master clock source to said plurality of interface control processors;

an external interface input port capable of receiving at least one external master synchronization signal from a second RF modem shelf in said fixed wireless access network; and

an external interface output port capable of receiving at least one of said internal master clock signal and said internal master framing signal from said primary master clock source and transmitting said at least one of said internal master clock signal and said internal master framing signal to said second RF modem shelf.

2. The timing distribution apparatus as set forth in claim 1 further comprising a secondary master clock source capable of generating said internal master clock signal and said internal master framing signal.

3. The timing distribution apparatus as set forth in claim 2 wherein said synchronization bus comprises a primary timing bus capable of distributing said internal master clock signal and said internal master framing signal from said primary master clock source and a secondary timing bus capable of distributing said internal master clock signal and said internal master framing signal from said secondary master clock source.

4. The timing distribution apparatus as set forth in claim 3 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said at least one external master synchronization signal.

5. The timing distribution apparatus as set forth in claim 4 wherein said secondary master clock source generates said internal master clock signal and said internal master framing signal from said at least one external master synchronization signal.

6. The timing distribution apparatus as set forth in claim 3 wherein said external interface input port is further capable of receiving a building integrated timing supply (BITS) reference signal from a locally disposed external clock source.

7. The timing distribution apparatus as set forth in claim 6 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said BITS reference signal.

8. The timing distribution apparatus as set forth in claim 7 wherein said secondary master clock source generates said internal master clock signal and said internal master framing signal from said BITS reference signal.

9. The timing distribution apparatus as set forth in claim 3 wherein said external interface input port is further capable of receiving a global positioning system (GPS) reference signal from an external GPS clock source.

10. The timing distribution apparatus as set forth in claim 9 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said GPS reference signal.

11. A fixed wireless access network comprising:

a plurality of transceiver base stations capable of bidirectional wireless communication with a plurality of wireless access devices disposed at a plurality of subscriber premises; and

a plurality of radio frequency (RF) modem shelves associated with said plurality of transceiver base stations, a first one of said plurality of RF modem shelves comprising a timing distribution apparatus for synchronizing the operations of a plurality of RF modems in said first RF modem shelf, wherein said timing distribution apparatus comprises;

a primary master clock source capable of generating an internal master clock signal and an internal master framing signal;

a plurality of interface control processors, each of said interface control processors capable of receiving said internal master clock signal and said internal master framing signal and capable of using said internal master clock signal and said internal master framing signal to synchronize a downlink transmission of one of said plurality of RF modems;

a synchronization bus capable of distributing said internal master clock signal and said internal master framing signal from said primary master clock source to said plurality of interface control processors;

an external interface input port capable of receiving at least one external master synchronization signal from a second RF modem shelf in said fixed wireless access network; and

an external interface output port capable of receiving at least one of said internal master clock signal and said internal master framing signal from said primary master clock source and transmitting said at least one of said internal master clock signal and said internal master framing signal to said second RF modem shelf.

12. The fixed wireless access network as set forth in claim 11 further comprising a secondary master clock source capable of generating said internal master clock signal and said internal master framing signal.

13. The fixed wireless access network as set forth in claim 12 wherein said synchronization bus comprises a primary timing bus capable of distributing said internal master clock signal and said internal master framing signal from said primary master clock source and a secondary timing bus capable of distributing said internal master clock signal and said internal master framing signal from said secondary master clock source.

14. The fixed wireless access network as set forth in claim 13 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said at least one external master synchronization signal.

15. The fixed wireless access network as set forth in claim 14 wherein said secondary master clock source generates said internal master clock signal and said internal master framing signal from said at least one external master synchronization signal.

16. The fixed wireless access network as set forth in claim 13 wherein said external interface input port is further capable of receiving a building integrated timing supply (BITS) reference signal from a locally disposed external clock source.

17. The fixed wireless access network as set forth in claim 16 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said BITS reference signal.

18. The fixed wireless access network as set forth in claim 17 wherein said secondary master clock source generates said internal master clock signal and said internal master framing signal from said BITS reference signal.

19. The fixed wireless access network as set forth in claim 13 wherein said external interface input port is further capable of receiving a global positioning system (GPS) reference signal from an external GPS clock source.

20. The fixed wireless access network as set forth in claim 19 wherein said primary master clock source generates said internal master clock signal and said internal master framing signal from said GPS reference signal.