System for controlling a switchmode power supply in a computer system by first coarsely and then finely adjusting a time-length signal

• US 6,804,788 B1
• Filed: 08/03/2000
• Issued: 10/12/2004
• Est. Priority Date: 08/03/2000
• Status: Expired due to Fees

• Current Assignee: Astec International Limited (Emerson Electric Company)
• Original Assignee: Astec America Incorporated (Emerson Electric Company)
• Inventors: Ling, Chen Wing, Lubomirsky, Vadim
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Du, Thuan
• Application Number:
  US09/632,179
• Time in Patent Office: 1,531 Days
• Field of Search: 713/300, 713/310, 713/320, 713/321, 713/323, 713/324, 713/330, 713/340, 327/143, 327/198, 327/544, 323/315, 365/226, 375/242, 375/355
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A pulse width modulation controlling circuit for a power supply and method for controlling a switchmode power supply in a computer is disclosed. The present invention accomplishes control over the switching of the power supply by coarsely and then finely adjusting a time-length signal.

Claims

1. A method for controlling a power supply in a computer comprising:

generating a time-length signal in a processing means;

transmitting a first portion of said time-length signal to a counting means, and a second portion of said time-length signal to a selection means;

counting to a number based on said first portion of said time-length signal received by said counting means;

outputting a coarse adjusted signal from said counting means after counting to said predetermined number;

selecting a delay from a delay means based on said second portion of said time-length signal received by said selection means;

delaying said coarse adjusted signal a predetermined length of time based on said selected delay in said delay means; and

outputting an output signal to said power supply in said computer after said predetermined delay.

2. The process of claim 1, wherein said process further comprises:

outputting said time-length signal from said processing means at a first voltage to a transforming means;

transforming said time-length signal from said first voltage to a second voltage;

outputting a selection output signal at said first voltage from said selection means to a second transforming means; and

transforming said selection output signal from said second voltage to said first voltage.

3. The process of claim 2, further comprising:

outputting said selection output signal to a power-converting means;

outputting said selection output signal from said second transforming means to a power-conditioning means; and

outputting said time-length signal to a second transforming means.

4. The process of claim 1, wherein said processor means, counting means, delay means, and selection means operate at a first voltage.

5. The process of claim 1, wherein said processor means operates at a first voltage, and said counting means, delay means, and selection means operates at a second voltage.

6. The process of claim 1, wherein the step of generating a time-length signal further comprises generating said time-length signal in a processor means.

7. The process of claim 1, wherein said counting means is a digital counting means.

8. The process of claim 7, wherein said digital counting means comprises a programmable logic device.

9. The process of claim 8, wherein said counting means comprises an oscillator means operating at a predetermined frequency.

10. The process of claim 9, wherein said oscillator means oscillates at approximately 125 MHz.

11. The process of claim 1, wherein said delay means delays in increments of 0.25 nanoseconds.

12. The process of claim 1, wherein said delay means is an analog delay means.

13. The process of claim 1, wherein said delay means is a digital delay means.

14. The process of claim 12, wherein said delay means comprises a plurality of inductors and capacitors connected in a series-parallel configuration.

15. The process of claim 1, wherein said selection means is a digital selection means.

16. The process of claim 1, wherein said selection means is a multiplexor.

17. The process of claim 1, wherein said counting means, said delay means and said selection means are disposed in said processing means.

18. A method for controlling a power supply comprising the steps of:

generating a power conversion signal;

controlling a power converter in accordance with the power conversion signal;

conditioning an output from the power converter to generate a conditioned output signal;

processing the conditioned output signal to generate a control signal, the step of processing comprising the steps of;

generating a time-length signal;

transmitting a first portion of said time-length signal to a counter, and a second portion of said time-length signal to a selector;

counting to a first predetermined number based on said first portion of said time-length signal;

outputting a coarse adjusted signal after counting to the predetermined number;

selecting a delay based on said second portion of said time-length signal;

delaying said coarse adjusted signal a predetermined period based on said selected delay; and

outputting a first control signal after delaying said coarse adjusted signal;

outputting a second control signal in accordance with the first control signal to control the step of generating a power conversion signal.

19. The method of claim 18 further comprising the steps of:

transforming the output from the power converter prior to the step of conditioning the output from the power converter; and

transforming the first control signal prior to the step of outputting a second control signal.

20. The method of claim 18 wherein the steps of generating a power conversion signal and outputting a second control signal occur at a first voltage, and the step of controlling a power converter, conditioning an output, and processing the conditioned output occur at a second voltage less than the first voltage.

21. A method for controlling a power supply in a computer comprising the steps of:

controlling a power converter in accordance with a power conversion signal;

conditioning an output from the power converter to generate a conditioned output signal;

processing the conditioned output signal to generate a control signal, the step of processing comprising the steps of;

generating a time-length signal;

transmitting a first portion of said time-length signal to a counter, and a second portion of said time-length signal to a selector;

counting to a first predetermined number based on said first portion of said time-length signal;

outputting a coarse adjusted signal after counting to the predetermined number;

selecting a delay based on said second portion of said time-length signal;

delaying said coarse adjusted signal a predetermined period based on said selected delay;

outputting a first control signal after delaying said coarse adjusted signal; and

generating the power conversion signal in accordance with the first control signal.

22. The method of claim 21 further comprising the steps of:

transforming the output from the power converter prior to the step of conditioning the output from the power converter; and

transforming the power conversion signal prior to the step of controlling the power converter.

23. The method of claim 21 wherein the steps of controlling a power converter occurs at a first voltage, and the step of conditioning an output, and processing the conditioned output occur at a second voltage less than the first voltage.