Error condition handling

• US 6,804,794 B1
• Filed: 02/28/2001
• Issued: 10/12/2004
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Robidoux, Gregory, Walton, John
• Primary Examiner(s): Baderman, Scott
• Application Number:
  US09/796,259
• Time in Patent Office: 1,322 Days
• Field of Search: 714/5, 714/41, 714/42, 709/318
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

In one embodiment of the present invention, a memory controller is provided that includes both a first processor and a second processor. If a memory device controlled by the controller indicates to the controller that an error condition exists in the device, either the first processor or the second processor is selected to handle the error condition. If the first processor is selected to handle the error condition, the first processor handles the error condition according to one or more statically preprogrammed error handling routines. Conversely, if the second processor is selected to handle the error condition, the second processor handles the error condition according to one or more dynamically programmable error handling routines.

Claims

1. Memory controller comprising:

a first processor that may be used to handle a memory device error condition according to one or more statically preprogrammed error handling routines; and

a second processor that may be used to handle the error condition according to one or more dynamically programmable error handling routines;

wherein the first processor and the second processor may be controlled so as to select which of the first processor and the second processor to handle the error condition.

2. Memory controller according to claim 1, further comprising:

a selector that selects the one of the first processor and the second processor that is used to handle the error condition.

3. Memory controller according to claim 1, wherein the first and second processor may be controlled by a device that is external to the controller so as to select which of the first processor and the second processor is used to handle the reported error condition.

4. Memory controller according to claim 3, wherein the error condition is reported to the memory controller by a memory device that is controlled by the memory controller, and the device that is external to the controller may be used to exchange data between the memory device and one of a computer system and at least one mass storage device.

5. Memory controller according to claim 1, also comprising a memory that, during operation of the controller, may store a first set of instructions received from a device external to the controller, the first set of instructions when executed by the second processor causing the second processor to handle the error condition in a first manner.

6. Memory controller according to claim 5, wherein, after the memory has received and stored the first set of instructions, the memory may store, during the operation of the controller, a second set of instructions received from the device, the second set of instructions being different from the first set of instructions, the second set of instructions when executed by the second processor causing the second processor to handle the error condition in a second manner, the first manner being different from the second manner.

7. Method of operating a memory controller, the memory controller including a first processor and a second processor, the method comprising:

selecting one of the first processor and the second processor to handle a memory device error condition;

wherein if the first processor is selected to handle the error condition, the first processor handles the error condition according to one or more statically preprogrammed error handling routines; and

if the second processor is selected to handle the error condition, the second processor handles the error condition according to one or more dynamically programmable error handling routines.

8. Method according to claim 7, wherein a selector comprised in the controller selects the one of the first processor and the second processor to handle the error condition.

9. Method according to claim 7, a device that is external to the controller selects the one of the first processor and the second processor to handle the error condition.

10. Method according to claim 9, wherein the error condition is reported to the memory controller by a memory device that is controlled by the memory controller, and the device that is external to the controller may be used to exchange data between the memory device and one of a computer system and at least one mass storage device.

11. Method according to claim 7, also comprising:

storing in a memory, during operation of the controller, a first set of instructions received from a device external to the controller, the first set of instructions when executed by the second processor causing the second processor to handle the error condition in a first manner.

12. Method according to claim 11, also comprising, after the memory has received and stored the first set of instructions:

storing in the memory, during the operation of the controller, a second set of instructions received from the device, the second set of instructions being different from the first set of instructions, the second set of instructions when executed by the second processor causing the second processor to handle the error condition in a second manner, the first manner being different from the second manner.

13. Computer-readable memory comprising computer-executable program instructions that when executed cause:

selecting of one of a first processor and a second processor to handle a memory device error condition, the first processor and the second processor being comprised in a controller;

wherein if the first processor is selected to handle the error condition, the first processor handles the error condition according to one or more statically preprogrammed error handling routines; and

if the second processor is selected to handle the error condition, the second processor handles the error condition according to one or more dynamically programmed error handling routines.

14. Computer-readable memory according to claim 13, wherein a selector comprised in the controller selects the one of the first processor and the second processor to handle the error condition.

15. Computer-readable memory according to claim 13, wherein a device that is external to the controller selects the one of the first processor and the second processor to handle the error condition.

16. Computer-readable memory according to claim 13, wherein the instructions, when executed, also cause:

storing in another memory, during operation of the controller, a first set of instructions received from a device external to the controller, the first set of instructions when executed by the second processor causing the second processor to handle the error condition in a first manner.

17. Computer-readable memory according to claim 16, wherein the instructions comprised in the computer-readable memory, when executed, also cause:

storing in the memory, during the operation of the controller, a second set of instructions received from the device, the second set of instructions being different from the first set of instructions, the second set of instructions when executed by the second processor causing the second processor to handle the error condition in a second manner, the first manner being different from the second manner.

18. A memory device comprising:

a memory array;

a memory controller coupled to the memory array by an error signal line, over which error signals indicating an error condition associated with the memory array are transmitted to the memory controller from the memory array, the memory controller comprising;

a first error handling module including a memory portion having at least one statically programmed error handling routine that enables the first error handling module to handle an error condition; and

a second error handling module including a memory portion for receiving at least one dynamically programmable error handling routine that enables the second error handling module to handle an error condition; and

a selection device for selecting which one of the first and second error handling modules for handling a particular error condition.