Bond wire tuning of RF power transistors and amplifiers

• US 6,806,106 B2
• Filed: 03/20/2001
• Issued: 10/19/2004
• Est. Priority Date: 03/20/2001
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Perugupalli, Prasanth, Dixit, Nagaraj, Leighton, Larry, Moller, Tom
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): MONDT, JOHANNES P
• Application Number:
  US09/813,604
• Publication Number:
  US 20020134993A1
• Time in Patent Office: 1,309 Days
• Field of Search: 438/5-6, 438/10-14, 438/17-18, 324/719, 257/664, 257/700, 257/728
• US Class Current: 438/17
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01083 Bismuth [Bi]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H03F 1/565 : using inductive elements
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence

Abstract

A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Claims

1. A method of manufacturing a power transistor circuit, comprising carrying out the following steps in the enumerated order:

(1) providing a substrate, said substrate comprising a pre-assembled power transistor circuit including a die secured to said substrate comprising a transistor having an input terminal, at least one input matching element and at least one input signal lead;

(2) measuring a performance characteristic of the transistor before connecting the transistor with the input matching element and input signal lead by means of a test network comprising connections with known inductances;

(3) using one or more wires to electrically couple the transistor input terminal to an input matching element, an input signal lead, or both; and

(4) setting the impedance of the one or more wires based at least in part on the measured transistor performance characteristic from step (2).

2. The method of claim 1, wherein the performance characteristic is defined, at least in part, by one or more of input capacitance, impedance, gain flatness, and signal phase shift.

3. The method of claim 1, wherein the impedance of the one or more wires is set by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

4. The method of claim 1, wherein the impedance of the one or more wires is set by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.

5. A method of manufacturing a power transistor circuit, comprising carrying out the following steps in the enumerated order:

(1) providing a substrate, said substrate comprising a pre-assembled power transistor circuit including a die secured to said substrate comprising a transistor having an output terminal, at least one input matching element and at least one input signal lead;

(2) measuring a performance characteristic of the transistor before connecting the transistor with the input matching element and input signal lead by means of a test network comprising connections with known inductances;

(3) using one or more wires to electrically couple the transistor output terminal to an output matching element, an output signal lead, or both; and

(4) setting the impedance of the one or more wires based at least in part on the measured transistor performance characteristic from step (2).

6. The method of claim 5, wherein the performance characteristic is defined, at least in part, by one or more of output capacitance impedance, gain flatness, and signal phase shift.

7. The method of claim 5, wherein the impedance of the one or more wires is set by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

8. The method of claim 5, wherein the impedance of the one or more wires is set by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.