×

Method and apparatus for wafer-level burn-in and testing of integrated circuits

  • US 6,806,494 B2
  • Filed: 05/27/2003
  • Issued: 10/19/2004
  • Est. Priority Date: 04/25/2000
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method of inspecting a burn-in testing result of a plurality of dies, comprising:

  • coupling an external power supply to at least one conductive pad disposed in an inactive region of a semiconductor wafer; and

    inspecting each of a plurality of burn-in indicating apparatuses, wherein each of said plurality of burn-in indicating apparatuses is coupled to a corresponding one die of a plurality of dies and is disposed on an active region of said semiconductor wafer, to determine whether a burn-in parameter has been satisfied.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×