Robust via structure and method

• US 6,806,579 B2
• Filed: 02/11/2003
• Issued: 10/19/2004
• Est. Priority Date: 02/11/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kaltalioglu, Erdem, Cowley, Andy, Stetter, Michael
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/364,190
• Publication Number:
  US 20040157442A1
• Time in Patent Office: 616 Days
• Field of Search: 257/762, 257/306, 438/629, 438/63, 438/687, 438/766, 438/786, 438/761
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a workpiece;

disposing a first insulating layer over the workpiece;

patterning the first insulating layer with a conductive line pattern;

filling the conductive line pattern with conductive material to form at least one conductive line within the first insulating layer, the conductive line including a top surface and at least one sidewall with an outside surface;

disposing a second insulating layer over the first insulating layer and the at least one conductive line;

removing a portion of the second insulating layer to expose at least a portion of the top surface of the conductive line;

removing a portion of the first insulating layer to expose at least a top portion of said outside surface of the at least one sidewall of the conductive line, wherein removing a portion of the second insulating layer and removing a portion of the first insulating layer forms a via opening wholly within the insulating layers; and

filling the via opening with conductive material to form a via, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of said outside surface of the at least one sidewall of the conductive line.

2. The method according to claim 1, wherein the conductive line at least one sidewall comprises an outwardly extending hook region, wherein filling the via opening with conductive material includes disposing the conductive material beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

3. The method according to claim 1, wherein removing a portion of the first insulating layer and forming a via opening comprise a single etch step.

4. The method according to claim 3, wherein the etch step comprises a reactive ion etch (RIE).

5. The method according to claim 1, further comprising a sputter etch prior to filling the via opening.

6. The method according to claim 5, wherein the sputter etch comprises removing the portion of the first insulating layer.

7. The method according to claim 1, wherein removing a portion of the first insulating layer comprises removing at least 100 Å

of the first insulating layer.

8. The method according to claim 1, wherein the first insulating layer comprises a first thickness, removing a portion of the first insulating layer comprises removing 5 to 15% of the first insulating layer first thickness.

9. The method according to claim 1, wherein filling the via opening with conductive material comprises filling the via opening with a material having a first coefficient of thermal expansion (CTE), wherein disposing a second insulating layer comprises depositing a material having a second CTE, the second CTE being higher than the first CTE.

10. The method according to claim 9, wherein the first CTE is 20 p.p.m/degrees C. or less, wherein the second CTE is 50 p.p.m/degrees C. or greater.

11. The method according to claim 9, wherein the first insulating layer comprises the second CTE material.

12. The method according to claim 1, wherein forming a second insulating layer comprises depositing a low-dielectric constant material having a dielectric constant of 3.6 or less, wherein the conductive line material comprises copper or aluminum.

13. The method according to claim 1, wherein forming at least one conductive line comprises patterning the first insulating layer with an opening for the at least one conductive line, depositing a fist conductive liner over the insulating layer, wherein the first conductive liner lines the opening including the sidewalls, and filling the opening over the first conductive liner with a first conductive fill material such that said via makes contact with the first conductive liner of said ton portion of the at least one sidewall of the conductive line;

and wherein filling the via opening comprises depositing a second conductive liner over the via opening, and filling the via opening over the second conductive liner with a second conductive fill material.

14. The method according to claim 13, wherein the first conductive fill material or the second conductive fill material are filled by plating.

15. The method according to claim 1 wherein forming a via opening comprises exposing the dielectric layer to an anisotropic etch.

37. The method according to claim 1 wherein said step of removing a portion of the first insulating layer further comprises removing said portion of the first insulating layer so that the conductive line material is not removed.

16. A method of forming a via of a semiconductor device, comprising:

providing a workpiece;

disposing a first insulating layer over the workpiece;

forming a hard mask over the first insulating layer;

patterning the hard mask and the first insulating layer, wherein patterned portions of the hard and the first insulating layer comprise sidewalls;

forming a first conductive liner over at least the sidewalls of the patterned hard mask and first insulating layer to define an outside surface;

forming a first conductive material over the first conductive liner, wherein a portion of the first conductive liner and a portion of the first conductive material comprise at least one conductive line, the conductive line including a top surface and at least one sidewall, wherein the conductive line at least one sidewall comprises an outwardly extending hook region;

forming a cap layer over the first insulating layer and the first conductive liner;

disposing a second insulating layer over the cap layer;

removing a portion of the second insulating layer and a portion of the cap layer to expose at least a portion of the top surface of the conductive line;

removing a portion of at least the hard mask to expose at least a top portion of said defined outside surface of the conductive liner covering the hard mask on the at least one sidewall of the conductive line, wherein removing a portion of at least the hard mask and removing a portion of the first insulating layer forms a via opening wholly within the hard mask and first insulating layer;

forming a second conductive liner over at least the second insulating layer; and

forming a second conductive material over the second conductive liner, wherein a portion of the second conductive liner and a portion of the second conductive material within the via opening form a via, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line, and wherein a portion of the via second conductive material is disposed beneath the conductive line hook region to form a locking region within the via proximate the conductive line hook region.

17. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first insulating layer over the workpiece;

forming at least one conductive line within the first insulating layer, the conductive line having a top surface and at least one sidewall defining an outside surface, wherein the conductive line at least one sidewall comprises an outwardly extending hook region;

forming a second insulating layer over the conductive line and the first insulating layer; and

forming at least one via within the second insulating layer over the conductive line, wherein the at least one via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of said defined outside surface of said at least one sidewall of the conductive line.

18. The method according to claim 17, wherein forming the at least one via comprises disposing a portion of the at least one via beneath the conductive line hook region, forming a locking region within the at least one via proximate the conductive line hook region.

19. The method according to claim 17, wherein the first insulating layer has a top surface, wherein forming the at least one via comprises forming at least one via that extends below the top surface of the first insulating layer by at least 100 Å

.

20. The method according to claim 17, wherein the first insulating layer comprises a first thickness and has a top surface, wherein forming the at least one via comprises forming at least one via that extends below the top surface of the first insulating layer by approximately 5 to 15% of the first insulating layer first thickness.

21. The method according to claim 17, wherein forming the at least one via comprises forming the at least one via comprising a material having a first coefficient of thermal expansion (CTE), and wherein forming the second insulating layer comprises forming a material having a second CTE, the second CTE being higher than the first CTE.

22. The method according to claim 21, wherein the first CTE is 20 p.p.m/degrees C. or less, wherein the second CTE is 50 p.p.m/degrees C. or greater.

23. The method according to claim 21, wherein the first insulating layer comprises the second CTE material.

24. The method according to claim 17, wherein forming the second insulating layer comprises forming a low-dielectric constant material having a dielectric constant of 3.6 or less, wherein forming the at least one conductive line comprises forming the at least one conductive line from copper or aluminum.

25. The method according to claim 17, wherein forming the at least one conductive line comprises forming a first conductive liner within the first insulating layer and disposing a first conductive fill material over the first conductive liner, and forming the at least one via comprises forming a second conductive liner within the second insulating layer and disposing a second conductive fill material over the second conductive liner.

26. The method according to claim 17, wherein the at least one conductive line comprises a second sidewall, and wherein forming the at least one via comprises forming at least one via that makes contact with at least a top portion of the second sidewall of the conductive line.

39. The method according to claim 17, wherein said step of forming one via within the second insulating layers further comprise forming said via such that material is not removed from said at least one sidewall of said conductive line.

27. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first insulting layer over the workpiece;

forming a hard mask over the first insulating layer, wherein portions of the first insulating layer and portions of the hard mask comprise sidewalls;

forming a conductive line within the first insulating layer and the hard mask, the conductive line including a liner disposed over at least the sidewalls of portions of the first insulating layer and portions of the hard mask and defining an outside surface, the conductive line including a fill material disposed over the liner, the fill material comprising copper, the conductive line having a top surface and at least one sidewall;

disposing a cap layer over at least the hard mask;

forming a second insulating layer over the cap layer, the second insulating layer comprising a low-k dielectric material; and

forming a via extending through the second insulating layer and the cap layer to abut at least a portion of the top surface of the conductive line, wherein the via extends through at least the hard mask to abut at least a top portion of the said defined outside surface of the liner disposed over at least one sidewall of the conductive line.

28. The method according to claim 27, wherein forming the conductive line comprises forming a conductive line having at least one sidewall comprising an outwardly extending hook region, wherein a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

29. The method according to claim 27, wherein the hard mask has a top surface, wherein forming the via comprises forming a via extending below the top surface of the hard mask by at least 100 Å

.

30. The method according to claim 27, wherein the hard mask comprises a first thickness and has a top surface, wherein forming the via comprises forming a via extending below the top surface of the hard mask by approximately 20-40% of the hard mask first thickness.

31. The method according to claim 27, wherein forming the via comprises forming a via comprising a material having a first coefficient of thermal expansion (CTE), wherein forming the second insulating layer comprises forming a material having a second CTE, the second CE being higher than the first CTE.

32. The method according to claim 31, wherein the first CTE is 20 p.p.m/degrees C. or less, wherein the second CTE is 50 p.p.m/degrees C. or greater.

33. The method according to claim 31, wherein the first insulating layer comprises the second CTE material.

34. The method according to claim 27, wherein forming the second insulating layer comprises forming a second insulating layer having a dielectric constant of 3.6 or less.

35. The method according to claim 27, wherein forming the via comprises forming a second conductive liner within the second insulating layer, and disposing a second conductive fill material over the second conductive liner.

36. The method according to claim 27, wherein the conductive line comprises a second sidewall, and wherein forming the via comprises forming a via that makes contact with at least a top portion of the second sidewall of the conductive line.

38. A method of manufacturing a semiconductor device, comprising:

providing a workpiece;

disposing a first insulating layer over the workpiece;

patterning the first insulating layer with a conductive line pattern;

filling the conductive line pattern with conductive material to form at least one conductive line within the first insulating layer, the conductive line including a top surface and at least one sidewall;

disposing a second insulating layer over the first insulating layer and the at least one conductive line;

removing a portion of the second insulating layer to expose at least a portion of the top surface of the conductive line;

removing a portion of the first insulating layer to expose at least a top portion of the at least one sidewall of the conductive line and such that the conductive line material is not removed, wherein removing a portion of the second insulating layer and removing a portion of the first insulating layer comprise forming a via opening; and

filling the via opening with conductive material to form a via, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line.

40. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first insulating layer over the workpiece;

forming at least one conductive line within the first insulating layer, the conductive line having a top surface and at least one sidewall, wherein the conductive line at least one sidewall comprises an outwardly extending hook region;

forming a second insulating layer over the conductive line and the first insulating layer; and

forming at least one via within the second insulating layer over the conductive line and within the first insulating layer such that material is not removed from said at least one sidewall of said conductive line, wherein the at least one via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line.