Multi-phase buck converter

• US 6,806,689 B2
• Filed: 03/18/2003
• Issued: 10/19/2004
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Schuellein, George, Crowther, Mark, Clavette, Dan
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): Laxton, Gary L.
• Application Number:
  US10/392,121
• Publication Number:
  US 20030178975A1
• Time in Patent Office: 581 Days
• Field of Search: 323/222, 323/223, 323/225, 323/272, 323/282, 363/65
• US Class Current: 323/272
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A buck converter for providing an output voltage to a load, including a plurality of output switch arrangements having respective output inductors coupled to an output capacitor, the switch arrangements being controllable to provide phase output currents to the output capacitor; a plurality of phase output arrangements respectively coupled to the output switch arrangements, the phase output arrangements being controllable to set the respective phase output currents supplied by the output switch arrangements; a phase control bus communicatively coupled to each of the phase output arrangements; and a phase control arrangement communicatively coupled to the phase control bus, the phase control arrangement being configured to control the phase output arrangements to set the respective phase output currents so that the output voltage approximates the desired voltage; wherein the phase control arrangement and the phase output arrangements are provided as respective integrated circuits.

Claims

1. A buck converter for providing an output voltage to a load, the output voltage being produced from an input voltage in accordance with a desired voltage, comprising:

an output capacitor, the output voltage being provided by the output capacitor;

a plurality of output switch arrangements having respective output inductors coupled to the output capacitor, the switch arrangements being controllable to provide respective phase output currents to the output capacitor through the respective output inductors;

a plurality of phase output arrangements respectively coupled to the output switch arrangements, the phase output arrangements being controllable to set the respective phase output currents supplied by the output switch arrangements;

a phase control bus communicatively coupled to each of the phase output arrangements; and

a phase control arrangement communicatively coupled to the phase control bus, the phase control arrangement being configured to control the phase output arrangements to set the respective phase output currents supplied by the output switch arrangements so that the output voltage approximates the desired voltage;

wherein the phase control arrangement and the phase output arrangements are provided as respective integrated circuits, and the phase control arrangement is configured to control the phase output arrangements via the phase control bus.

2. The buck converter according to claim 1, wherein each of the output switch arrangements includes a high-side switch and a low-side switch coupled to the high-side switch via a respective switch node, the output inductor of each of the output switch arrangements being coupled to the respective switch node.

3. The buck converter according to claim 2, wherein the phase control bus includes a phase timing signal, a PWM control signal, and an average inductor current signal, each of the phase output arrangements includes a start-time arrangement configured to switch on the high-side switch of the respective output switch arrangement in accordance with the phase timing signal, each of the phase output arrangements includes a charge-on duration arrangement configured to switch off the high-side switch of the respective output switch arrangement in accordance with the PWM control signal.

4. The buck converter according to claim 3, wherein the start-time arrangement includes a phase timing comparator electrically coupled to the phase timing signal and a one-shot pulse generator electrically coupled to an output of the phase timing comparator, the one-shot pulse generator configured to produce a clock pulse in accordance with the phase timing signal and a set-point voltage, the clock pulse switching on the high-side switch.

5. The buck converter according to claim 4, wherein the set-point voltage is provided by a voltage divider connected between a reference voltage and a ground voltage.

6. The buck converter according to claim 3, wherein the charge-on duration arrangement includes a ramp generator electrically coupled to the current difference signal and a charge-on duration amplifier electrically coupled to the ramp generator and the PWM control signal, the ramp generator being configured to produce a ramp output signal in accordance with the current difference signal and a default voltage, the charge-on duration amplifier configured to switch off the high-side switch in accordance with the ramp output signal and the PWM control signal.

7. The buck converter according to claim 6, wherein the ramp generator includes a ramp capacitor electrically coupled to the ramp output signal, a clamp circuit electrically coupled to the ramp output signal and to the default voltage, and a programmable current source electrically coupled between the ramp output signal and a ground voltage, the programmable current source being controllable in accordance with the current difference signal.

8. The buck converter according to claim 7, wherein the phase control bus includes a signal characterizing the desired voltage, each of the phase output arrangements receiving the signal characterizing the desired voltage, the default voltage being set in accordance with the signal characterizing the desired voltage.

9. The buck converter according to claim 7, wherein the ramp generator further includes a phase error detect arrangement configured to produce a phase error signal if the phase output arrangement is incapable of providing a phase output current to match the average inductor current signal.

10. The buck converter according to claim 6, wherein the charge-on duration arrangement further includes a body-brake detect amplifier configured to switch off the high-side switch and the low-side switch in response to at least one of a request for a lower desired voltage and a decrease in a current demand of the load.

11. The buck converter according to claim 10, wherein the request for the lower desired voltage and the decrease in the current demand of the load are determined in accordance with the PWM control signal.

12. The buck converter according to claim 3, wherein each of the phase output arrangements further includes a current sense arrangement electrically connected to a first node and a second node of the respective output inductor and to the average inductor current signal, the current sense arrangement configured to detect the respective phase output current and to generate a current difference signal in accordance with the average inductor current signal and the respective phase output current.

13. The buck converter according to claim 12, wherein the current sense arrangement includes a current detection arrangement connected to the first and second nodes of the respective output inductor and a current comparator electrically connected to an output of the current sense arrangement and to the average inductor current signal, the current sense arrangement generating the current difference signal in accordance with the output of the current sense arrangement and the average inductor current signal.

14. The buck converter according to claim 13, wherein the current detection arrangement includes a current sense amplifier, a resistor R_CS electrically coupled between a positive input of the current sense amplifier and the first node, and a capacitor C_CS electrically coupled between the positive input and a negative input of the current sense amplifier, the second node being connected to the negative input, a time constant of the resistor R_CS and the capacitor C_CS being approximately equal to a time constant of the respective output inductor.

15. The buck converter according to claim 3, wherein the phase control arrangement includes a phase timing arrangement and a PWM arrangement, the phase timing arrangement configured to produce the phase timing signal and the PWM arrangement configured to produce the PWM control signal.

16. The buck converter according to claim 15, wherein the phase timing arrangement includes a programmable oscillator arrangement and a periodic waveform generator electrically coupled to the programmable oscillator arrangement, a frequency of the programmable oscillator arrangement be selectable via a frequency select input, the periodic waveform generator producing the phase timing signal in accordance with the frequency of the programmable oscillator arrangement.

17. The buck converter according to claim 15, wherein the PWM arrangement includes a digital-to-analog converter configured to produce a variable characterizing the desired voltage in accordance with a plurality of digital VID signals, a high-gain error amplifier electrically coupled to the variable characterizing the desired voltage and the output voltage, the high-gain error amplifier producing the PWM control signal in accordance with the variable characterizing the desired voltage and the output voltage.

18. The buck converter according to claim 15, wherein the PWM arrangement further includes droop circuitry configured to modify the PWM control signal, such that the output voltage is reduced proportionally to an increase in a current flow through the load.

19. The buck converter according to claim 15, wherein the PWM arrangement further includes body-brake circuitry configured to modify the PWM control signal, such that the phase output arrangements switch off the high-side and low-side switches of the respective output switch arrangements in response to a request for a lower desired output voltage.

20. The buck converter according to claim 3, wherein each of the phase control arrangement and the phase output arrangements includes a respective over-temperature detect circuit configured to produce a VRHOT signal if a temperature of the respective integrated circuit rises above a respective temperature threshold.

21. A phase output arrangement of a buck converter, the phase output arrangement being electrically coupleable to an output switch arrangement having an output inductor, a high-side switch, and a low-side switch, the buck converter providing an output voltage to a load via an output capacitor electrically coupled to the output inductor, the output voltage being produced from an input voltage in accordance with a desired voltage, the phase output arrangement comprising:

a start-time arrangement configured to switch on the high-side switch of the output switch arrangement in accordance with a phase timing signal; and

a charge-on duration arrangement configured to switch off the high-side switch of the output switch arrangement in accordance with a PWM control signal;

wherein the phase output arrangement is implemented as a separate integrated circuit, and the phase output arrangement is configured to be communicatively coupled with a phase control arrangement via a phase control bus, the phase timing signal and the PWM control signal being communicated by the phase control arrangement via the phase control bus.

22. The phase output arrangement according to claim 21, wherein the start-time arrangement includes a phase timing comparator electrically coupled to the phase timing signal and a one-shot pulse generator electrically coupled to an output of the phase timing comparator, the one-shot pulse generator configured to produce a clock pulse in accordance with the phase timing signal and a set-point voltage, the clock pulse switching on the high-side switch.

23. The phase output arrangement according to claim 22, wherein the set-point voltage is provided by a voltage divider connected between a reference voltage and a ground voltage.

24. The phase output arrangement according to claim 21, wherein the charge-on duration arrangement includes a ramp generator electrically coupled to the current difference signal and a charge-on duration amplifier electrically coupled to the ramp generator and the PWM control signal, the ramp generator being configured to produce a ramp output signal in accordance with the current difference signal and a default voltage, the charge-on duration amplifier configured to switch off the high-side switch in accordance with the ramp output signal and the PWM control signal.

25. The phase output arrangement according to claim 24, wherein the ramp generator includes a ramp capacitor electrically coupled to the ramp output signal, a clamp circuit electrically coupled to the ramp output signal and to the default voltage, and a programmable current source electrically coupled between the ramp output signal and a ground voltage, the programmable current source being controllable in accordance with the current difference signal.

26. The phase output arrangement according to claim 25, wherein the phase control bus includes a signal characterizing the desired voltage, the phase output arrangement receiving the signal characterizing the desired voltage, the default voltage being set in accordance with the signal characterizing the desired voltage.

27. The phase output arrangement according to claim 25, wherein the ramp generator further includes a phase error detect arrangement configured to produce a phase error signal if the phase output arrangement is incapable of providing a phase output current to match an average inductor current signal characterizing an average current provided by at least one other phase output arrangement.

28. The phase output arrangement according to claim 24, wherein the charge-on duration arrangement further includes a body-brake detect amplifier configured to switch off the high-side switch and the low-side switch in response to at least one of a request for a lower desired voltage and a decrease in a current demand of the load.

29. The phase output arrangement according to claim 28, wherein the request for the lower desired voltage and the decrease in the current demand of the load are determined in accordance with the PWM control signal.

30. The phase output arrangement according to claim 21, further comprising:

a current sense arrangement electrically connected to a first node and a second node of the output inductor and to an average inductor current signal characterizing an average current provided by at least one other phase output arrangement, the current sense arrangement configured to detect a phase output current and to generate a current difference signal in accordance with the average inductor current signal and the respective phase output current.

31. The phase output arrangement according to claim 30, wherein the current sense arrangement includes a current detection arrangement connected to the first and second nodes of the output inductor and a current comparator electrically connected to an output of the current sense arrangement and to the average inductor current signal, the current sense arrangement generating the current difference signal in accordance with the output of the current sense arrangement and the average inductor current signal.

32. The phase output arrangement according to claim 31, wherein the current detection arrangement includes a current sense amplifier, a resistor R_CS electrically coupled between a positive input of the current sense amplifier and the first node, and a capacitor C_CS electrically coupled between the positive input and a negative input of the current sense amplifier, the second node being connected to the negative input, a time constant of the resistor R_CS and the capacitor C_CS being approximately equal to a time constant of the output inductor.

33. A phase control arrangement of a buck converter, the phase control arrangement being electrically coupleable to a phase control bus for controlling at least one phase output arrangement, the buck converter providing an output voltage to a load via an output capacitor, the output voltage being produced from an input voltage in accordance with a desired voltage, the phase control arrangement comprising:

a phase timing arrangement; and

a PWM arrangement;

wherein the phase timing arrangement is configured to communicate a phase timing signal to the phase output arrangement via the phase control bus, the PWM arrangement is configured to communicate a PWM control signal to the phase output arrangement via the phase control bus, and the phase control arrangement is implemented as a separate integrated circuit.

34. The phase control arrangement according to claim 33, wherein the phase timing arrangement includes a programmable oscillator arrangement and a periodic waveform generator electrically coupled to the programmable oscillator arrangement, a frequency of the programmable oscillator arrangement be selectable via a frequency select input, the periodic waveform generator producing the phase timing signal in accordance with the frequency of the programmable oscillator arrangement.

35. The buck converter according to claim 33, wherein the PWM arrangement includes a digital-to-analog converter configured to produce a variable characterizing the desired voltage in accordance with a plurality of digital VID signals, a high-gain error amplifier electrically coupled to the variable characterizing the desired voltage and the output voltage, the high-gain error amplifier producing the PWM control signal in accordance with the variable characterizing the desired voltage and the output voltage.

36. The buck converter according to claim 33, wherein the PWM arrangement further includes droop circuitry configured to modify the PWM control signal, such that the output voltage is reduced proportionally to an increase in a current flow through the load.

37. The buck converter according to claim 33, wherein the PWM arrangement further includes body-brake circuitry configured to modify the PWM control signal, such that the phase output arrangement switches off a high-side and a low-side switch of a respective output switch arrangements in response to a request for a lower desired output voltage.

38. The buck converter according to claim 33, further comprising:

an over-temperature detect circuit configured to produce a VRHOT signal if a temperature of the integrated circuit rises above a temperature threshold.

39. A phase output arrangement of a buck converter, the buck converter including a phase control arrangement, the phase output arrangement being electrically coupleable to an output switch arrangement having an output inductor, a high-side switch, and a low-side switch, the buck converter providing an output voltage to a load via an output capacitor electrically coupled to the output inductor, the output voltage being produced from an input voltage in accordance with a desired voltage, the phase output arrangement comprising:

a circuit arrangement configured to be communicatively coupled to the phase control arrangement via a phase control bus, the circuit arrangement being configured to be controlled by the phase control arrangement via the phase control bus so that the output switch arrangement generates the output voltage to approximate the desired voltage;

wherein the phase output arrangement is implemented as a separate integrated circuit.

40. A phase control arrangement of a buck converter, the buck converter including at least one phase output arrangement, the phase output arrangement being electrically coupled to an output switch arrangement having an output inductor, a high-side switch, and a low-side switch, the buck converter providing an output voltage to a load via an output capacitor electrically coupled to the output inductor, the output voltage being produced from an input voltage in accordance with a desired voltage, the phase control arrangement comprising:

a circuit arrangement configured to communicatively couple to the phase control arrangement via a phase control bus to control the phase control arrangement so that the output switch arrangement generates the output voltage to approximate the desired voltage;

wherein the phase control arrangement is implemented as a separate integrated circuit.