Multimode output stage converting differential to single-ended signals using current-mode input signals

• US 6,806,771 B1
• Filed: 05/31/2002
• Issued: 10/19/2004
• Est. Priority Date: 06/01/2001
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Li, Jian, Klein, Hans W., Hildebrant, Paul
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US10/159,681
• Time in Patent Office: 872 Days
• Field of Search: 330/51, 330/278, 330/284, 330/282, 330/311
• US Class Current: 330/284
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45458 the CSC comprising one or more capacitors
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45748 by using a feedback circuit
• CPC Class Codes: H03F 3/45973 by using a feedback circuit
• CPC Class Codes: H03G 3/001 Digital control of analog signals

Abstract

An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches. The CLDAC uses a digital-to-analog converter (DAC) to perform offset calibration at the differential input of the output amplifier. In addition, the output block is configured to be operational in a number of user-selectable modes, including, in one embodiment, one or more of: a linear (NORM) mode, a comparator (COMP) mode, and an integrator (INT) mode. An amplifier in the output block is variously reconfigured to achieve the selected mode of operation. Also, the output block accommodates an autocalibration (CAL) technique by clamping the single-ended output stage and balancing, through operation of the CLDAC, signals at an input node and at an interstage node of the amplifier.

Claims

1. A programmable gain stage comprising:

an amplifier having a differential, current-mode input and a single-ended voltage-mode output;

a first programmable feedback network coupled between the amplifier input and a reference potential (GND);

a second programmable feedback network coupled between the amplifier input and the amplifier output; and

a mode control input for receiving a mode control signal that determines the mode of operation of the gain stage; and

a mode control switch coupled to the amplifier input, to the first feedback network, and to the second feedback network.

2. A programmable gain stage as defined in claim 1, wherein the first feedback network includes a resistance coupled to the amplifier input through the mode control switch.

3. A programmable gain stage as defined in claim 2, wherein the second feedback network includes a second resistance coupled to the amplifier input through the mode control switch.

4. A programmable gain stage as defined in claim 3, wherein the first resistance and the second resistance are programmable.

5. A programmable gain stage as defined in claim 1, wherein the first feedback network includes a programmable capacitance coupled to the amplifier input.

6. A program gain stage as defined in claim 1, wherein the second feedback network includes a programmable capacitance coupled to the amplifier input.

7. A programmable gain stage as defined in claim 6, wherein the first feedback network includes a programmable capacitance coupled to the amplifier input.

8. A programmable gain stage as defined in claim 1, wherein the mode control switch is operable In response to the mode control signal to cause the gain stage to operate alternatively in a comparator mode or in an integrator mode.

9. A programmable gain stage as defined in claim 8, wherein the mode control switch comprises:

a first semiconductor device coupled to the mode control input and coupled between the first feedback network and an noninverting input of the amplifier, and

a second semiconductor device coupled to the mode control input and coupled between the second feedback network and an inverting input of the amplifier.

10. A programmable gain stage as defined in claim 9, wherein the mode control switch Is coupled to the mode control signal through a logic circuit.

11. A programmable gain stage as defined in claim 10, wherein the semiconductor devices are MOS transistors.

12. A programmable gain stage as defined in claim 11, wherein the first feedback network includes a resistance coupled to the amplifier input through the mode control switch.

13. A programmable gain stage as defined in claim 11, wherein the second feedback network includes a second resistance coupled to the amplifier input through the mode control switch.

14. A programmable gain stage as defined in claim 13, wherein the first resistance and the second resistance are programmable.

15. A programmable gain stage as defined in claim 11, wherein the first feedback network includes a programmable capacitance coupled to the amplifier input.

16. A programmable gain stage as defined in claim 11, wherein the second feedback network includes a programmable capacitance coupled to the amplifier input.

17. A programmable gain stage as defined in claim 16, wherein the first feedback network includes a programmable capacitance coupled to the amplifier input.

18. A programmable gain stage as defined in claim 11, wherein the mode control switch is operable in response to the mode control signal to cause the gain stage to operate alternatively in a comparator mode or in an integrator mode.

19. A method of selecting a mode of operation of a programmable gain-stage that includes:

(i) an amplifier having a differential, current-mode input and a single-ended voltage-mode output;

(ii) a feedback network that includes a feedback resistance and a programmable capacitance;

(iii) a mode-control input;

(iv) a mode-control switch coupled to the mode-control input, the amplifier input, and the feedback network; and

(v) a CAPCNTRL input, THE METHOD COMPRISING;

applying a mode control signal to the mode-control input;

distributing a signal derived from the mode-control signal to the mode-control switch; and

applying a CAPCNTRL signal to the CAPCNTRL input, the CAPCNTRL signal corresponding to the mode of operation of the gain-stage.

20. A method as defined in claim 19, wherein mode-control signal is a COMP signal that causes the feedback resistance to be disconnected from the amplifier input.

21. A method as defined in claim 20, further comprising:

applying a CAPCNTRL signal that causes programmable capacitance to assume a minimum value.

22. A method as defined in claim 21, further comprising:

activating a CLAMP coupled to the input of the amplifier.

23. A method as defined in claim 22, further comprising:

activating an interstage clamp coupled to an interstage node of the amplifier.

24. A method as defined in claim 23, further comprising:

disconnecting a Miller capacitance associated with an output stage of the amplifier.

25. A method as defined in claim 19, wherein the mode-control signal in an INT signal that causes the feedback resistance to be disconnected from the amplifier unit.

26. A method as defined in claim 25, further comprising:

establishing an integrator time constant through a CAPCNTRL signal applied to the CAPCNTRL input.

27. A programmable gain stage operable in response to a mode control signal, the gain stage comprising:

an amplifier having a current-mode inverting input, a current-mode noninverting input, and a single-ended voltage-mode output;

a mode control switch having a node responsive to the mode control signal;

a first feedback network coupled to the amplifier output, the amplifier inverting input, and the mode control switch; and

a second feedback network coupled to a reference node, the amplifier noninverting input, and the mode control switch.

28. A programmable gain stage as defined in claim 27, wherein the first feedback network comprises a programmable capacitance coupled between the amplifier output and the inverting input and comprises a resistance coupled to the inverting input through the mode control switch.

29. A programmable gain stage as defined in claim 27, wherein the second feedback network comprises a programmable capacitance coupled between GND and the noninverting input and comprises a resistance coupled to the noninverting input through the mode control switch.

30. A programmable gain stage as defined in claim 28, wherein the second feedback network comprises a programmable capacitance coupled between GND and the noninverting input and comprises a resistance coupled to the noninverting input through the mode control switch.

31. A programmable gain stage as defined in claim 27, wherein the mode control switch comprises:

a first semiconductor device coupled to the mode control signal and coupled between the first feedback network and an inverting input of the amplifier; and

a second semiconductor device coupled to the mode control signal and coupled between the second feedback network and a noninverting input of the amplifier.

32. A programmable gain stage as defined in claim 27, wherein the mode control switch is coupled to a mode control input through a logic gate.

33. A programmable gain stage as defined in claim 31, wherein the semiconductor devices are MOS transistors.

34. A programmable gain stage as defined in claim 27, wherein the mode control signal is operable to cause the programmable gain stage to operate alternatively in an integrator mode or in a comparator mode.

35. A programmable gain stage as defined in claim 34, wherein the first feedback network comprises a programmable capacitance coupled between the amplifier output and the inverting input and comprises a resistance coupled to the inverting input through the mode control switch.

36. A programmable gain stage as defined in claim 34, wherein the second feedback network comprises a programmable capacitance coupled between GND and the noninverting input and comprises a resistance coupled to the noninverting input through the mode control switch.

37. A programmable gain stage as defined in claim 35, wherein the second feedback network comprises a programmable capacitance coupled between GND and the noninverting input and comprises a resistance coupled to the noninverting input through the mode control switch.

38. A programmable gain stage as defined in claim 34, further comprising:

means coupled to the mode control signal and to the amplifier inputs for avoiding slow recovery of the programmable gain stage from an overdue condition in the comparator mode.

39. A multimode amplifier stage for an analog integrated circuit, the amplifier stage comprising:

an input stage having a summing node for a differential, current-mode input signal;

an output stage having an output node for providing a single-ended voltage;

an interstage node;

a reference node;

a mode control input for coupling to a mode control signal that determines the mode of operation of the amplifier stage;

a programmable feedback network coupled between the output node and the summing node; and

a mode control switch coupled to the summing node and to the programmable feedback network.

40. A multimode amplifier stage as defined in claim 39, wherein the mode control switch is operable in response to a mode control signal to cause the gain-stage to operate, alternatively, in a linear mode, a comparator mode, or an integrator mode.

41. A multimode amplifier stage as defined in claim 40, further comprising:

a CMFB coupled to the summing node for facilitating conversion of a differential-current input to single ended voltage output;

a CLAMP coupled to the summing node to avoid slow recovery from an overdrive condition in the comparator mode.

42. A multimode amplifier stage as defined in claim 40, wherein the programmable feedback network comprises a resistance and a capacitive array and wherein the gain-stage is operable, in response to the mode control signal, in an integrator mode whereby the resistance is disconnected from the summing node and is operable, in response to mode control signal in a comparator mode whereby both the resistance and the capacitance are disconnected from the summing node.

43. A multimode amplifier stage as defined in claim 42, further comprising a clamp coupled to the interstage node, the clamp selectably conductive in response to the mode control signal to limit the voltage swing at the interstage node.

44. A multimode amplifier stage as defined in claim 39, wherein the amplifier stage is operable in an auto-cal mode whereby the output stage is disabled and the output of the input stage, at the interstage node, is coupled to a latching comparator.

45. A multimode amplifier stage as defined in claim 44, further comprising a nested Miller capacitance selectable coupled to the output stage.

46. A multimode amplifier stage as defined in claim 45, wherein the nested Miller capacitance is disconnected in the comparator mode.

47. A multimode amplifier stage as defined in claim 39, further comprising:

a first clamp coupled to the summing node;

a second clamp coupled to the interstage node; and

a nested Miller capacitance selectably coupled to the second stage.

48. A multimode amplifier stage as defined in claim 47, wherein the mode control switch is operable in response to a mode control signal to cause the gain-stage to operate, alternatively, in a linear mode, a comparator mode, or an integrator mode.

49. A multimode amplifier stage as defined in claim 48, wherein the programmable feedback network comprises a resistance and a capacitive array and wherein the gain-stage is operable, in response to the mode control signal, in an integrator mode whereby the resistance is disconnected from the summing node and is operable, in response to mode control signal in a comparator mode whereby both the resistance and the capacitance are disconnected from the summing node.

50. A multimode amplifier stage as defined in claim 49, further comprising a clamp coupled to the interstage node, the clamp selectably conductive in response to the mode control signal to limit the voltage swing at the interstage node.

51. A multimode amplifier stage as defined in claim 48, wherein the amplifier stage is operable in an auto-cal mode whereby the output stage is disabled and the output of the input stage, at the interstage node, is coupled to a latching comparator.

52. A multimode amplifier stage as defined in claim 51, wherein the nested Miller capacitance is disconnected in the comparator mode.

53. A programmable gain stage comprising:

an amplifier having a differential, current-mode input and a single-ended voltage-mode output;

a programmable feedback network coupled to the amplifier input;

a mode control input for receiving a mode control signal that determines the mode of operation of the gain stage; and

a mode control switch coupled to the mode control input, the amplifier input and the feedback network.

54. A programmable gain stage as defined in claim 53, wherein the mode control switch comprises a semiconductor device coupled to the mode control input and coupled between the feedback network and the amplifier input.

55. A programmable gain stage as defined in claim 53, wherein the amplifier input comprises an inverting input and a noninverting input, and the semiconductor device is coupled between the feedback network and at least one of the inverting and noninverting inputs.

56. A multimode amplifier stage for an analog integrated circuit, the amplifier stage comprising:

an input stage having a summing node;

an output stage having an output node;

an interstage node; and

a mode control input for coupling to a mode control signal that determines the mode of operation of the amplifier stage,

wherein the amplifier stage is operable in an auto-cal mode whereby the output stage is disabled and the output of the input stage, at the interstage node, is coupled to a latching comparator.

57. A multimode amplifier stage as defined in claim 56, including a programmable feedback network coupled between the output node and the summing node.

58. A multimode amplifier stage as defined in claim 57, including a mode control switch coupled to the summing node and to the programmable feedback network.