In-plane switching mode liquid crystal display device having common lines crossing gate links
First Claim
1. An in-plane switching mode liquid crystal display device comprising:
- a plurality of data lines for applying data signals to a thin film transistor array;
a plurality of gate lines for applying gate signals to the thin film transistor array;
a plurality of gate links extended from the plurality of gate lines into an outer area of the thin film transistor array; and
a plurality of common voltage lines, being provided in such a manner to cross the plurality of gate links, for applying a common voltage to a liquid crystal at the outer area of the thin film transistor array to reduce a gate voltage at the plurality of gate links, wherein the plurality of common voltage lines are arranged parallel to the plurality of gate lines.
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Accused Products
Abstract
A liquid crystal display device that is capable of preventing a deterioration of liquid crystal generated at the outer area of an IPS mode TFT array. In the device, a plurality of data lines apply data signals to a thin film transistor array and a plurality of gate lines apply gate signals to the thin film transistor array. A plurality of gate links is extended from the gate lines into the outer area of the thin film transistor array. A plurality of common voltage lines is provided in such a manner to cross the gate links to apply a common voltage to the thin film transistor array. Accordingly, a deterioration of liquid crystal caused by the gate voltage at the outer area of the TFT array can be prevent to eliminate a generation of stain.
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Citations
15 Claims
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1. An in-plane switching mode liquid crystal display device comprising:
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a plurality of data lines for applying data signals to a thin film transistor array;
a plurality of gate lines for applying gate signals to the thin film transistor array;
a plurality of gate links extended from the plurality of gate lines into an outer area of the thin film transistor array; and
a plurality of common voltage lines, being provided in such a manner to cross the plurality of gate links, for applying a common voltage to a liquid crystal at the outer area of the thin film transistor array to reduce a gate voltage at the plurality of gate links, wherein the plurality of common voltage lines are arranged parallel to the plurality of gate lines. - View Dependent Claims (2, 3, 4)
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5. An in-plane switching mode liquid crystal display device, comprising:
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first and second substrates;
a plurality of data lines;
a plurality of gate lines perpendicular to the data lines;
a plurality of thin film transistors at crossing points of the data and gate lines and forming a thin film transistor array on the first substrate;
a plurality of gate links extended from the plurality of gate lines into an area outside of the thin film transistor array; and
a plurality of common voltage lines parallel to the gate lines and crossing the gate links, wherein the plurality of common voltage lines are configured to apply a common voltage to a liquid crystal at the area outside the thin film transistor array to reduce a gate voltage at the plurality of gate links. - View Dependent Claims (6, 7, 8)
a plurality of gate pads connected to the gate links and electrically disposed between the gate links and an external power source; and
a plurality of common voltage pads connected to the common voltage lines and electrically disposed between the common voltage lines and the external power source.
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7. The in-plane switching liquid crystal display device of claim 6, wherein the gate pads are located in the area outside of the thin film transistor array.
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8. The in-plane switching liquid crystal display device of claim 6, wherein the common voltage pads are located in the area outside of the thin film transistor array.
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9. An in-plane switching mode liquid crystal display device comprising:
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a plurality of data lines for applying data signals to a thin film transistor array;
a plurality of gate lines for applying gate signals to the thin film transistor array;
a plurality of signal pads in a signal pad area outside the thin film transistor array;
a plurality of gate links extended from the gate lines; and
a plurality of common lines extending to cross the plurality of the gate links between the signal pads and the thin film transistor array, wherein the plurality of common lines are configured to apply a common voltage to a liquid crystal at the area outside the thin film transistor array to reduce a gate voltage at the signal pad area, wherein the plurality of common lines are arranged parallel to the plurality of gate lines. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification