Enhanced storage states in an memory

• US 6,807,080 B2
• Filed: 05/17/2002
• Issued: 10/19/2004
• Est. Priority Date: 05/17/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.), Texas Instruments, Inc.
• Original Assignee: Agilent Technologies, Inc., Texas Instruments, Inc.
• Inventors: Summerfelt, Scott Robert, McAdams, Hugh Pryor, Rickes, Jurgen Thomas
• Primary Examiner(s): Le, Thong Q.
• Application Number:
  US10/150,744
• Publication Number:
  US 20030214830A1
• Time in Patent Office: 886 Days
• Field of Search: 365/145, 365/226, 365/227, 365/104, 365/149, 365/198.04, 365/65
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A memory with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

Claims

1. A memory, comprising:

storage cell having a storage structure capable of switching storage states;

programming circuit that writes the storage cell by applying a first voltage to a first node of the storage structure and applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

2. The memory of claim 1, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.

3. The memory of claim 1, wherein the second voltage is preselected such that an overall voltage drop across the storage structure is substantially equal to a supply voltage in the memory.

4. The memory of claim 1, wherein the storage cell includes an access transistor coupled to the first node of the storage structure.

5. The memory of claim 4, wherein the programming circuit comprises:

means for switching on the access transistor such that the access transistor passes the first voltage to the first node;

means for applying the second voltage to the second node such that the second voltage compensates for a threshold voltage loss in the access transistor.

6. The memory of claim 1, wherein the storage structure is a ferroelectric capacitor coupled between a storage node of the storage cell and a plate line to the storage cell.

7. The memory of claim 6, wherein the programming circuit comprises:

means for applying the first voltage to the storage node such that the first voltage is a positive voltage;

means for applying the second voltage to the plate line such that second voltage is a negative voltage.

8. The memory of claim 7, wherein a magnitude of the second voltage is preselected such that an overall voltage drop across the ferroelectric capacitor is substantially equal to a supply voltage in the memory.

9. The memory of claim 8, wherein the means for applying the first voltage includes an access transistor such that the magnitude is preselected in response to a voltage loss in the access transistor.

10. A method for writing a storage cell in a memory, comprising the steps of:

applying a first voltage to a first node of a storage structure in the storage cell;

applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

11. The method of claim 10, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.

12. The method of claim 10, further comprising the step of selecting the second voltage such that an overall voltage drop across the storage structure is substantially equal to a supply voltage in the memory.

13. The method of claim 10, wherein the steps of applying the first and second voltages comprise the steps of:

switching on the access transistor such that the access transistor passes the first voltage to the first node;

applying the second voltage to the second node such that the second voltage compensates for a threshold voltage loss in the access transistor.

14. The method of claim 10, wherein the storage structure is a ferroelectric capacitor coupled between a storage node of the storage cell and a plate line to the storage cell.

15. The method of claim 14, wherein the steps of applying the first and second voltages comprise the steps of:

applying the first voltage to the storage node such that the first voltage is a positive voltage;

applying the second voltage to the plate line such that second voltage is a negative voltage.

16. The method of claim 15, further comprising the step of selecting a magnitude of the second voltage such that an overall voltage drop across the ferroelectric capacitor is substantially equal to a supply voltage in the memory.

17. The method of claim 16, wherein the step of selecting comprises the step of selecting the magnitude in response to a voltage loss in an access transistor of the storage cell.

18. A memory, comprising:

storage structure having a storage node coupled to an access transistor and a node coupled to a plate line;

programming circuit that writes the storage structure by applying a positive voltage to the access transistor and by applying a negative voltage to the plate line such that a magnitude of the negative voltage is selected to compensate for an amount of loss of the positive voltage caused by the access transistor.

19. The memory of claim 18, wherein the negative voltage compensates for a threshold voltage loss in the access transistor.

20. The memory of claim 18, wherein the magnitude of the negative voltage is selected such that an overall voltage drop across the storage structure is substantially equal to a supply voltage in the memory.