Method of reconfiguration of radio parameters for power-aware and adaptive communications

• US 6,807,227 B2
• Filed: 10/25/2001
• Issued: 10/19/2004
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: OL Security LLC (Intellectual Ventures LLC)
• Original Assignee: Rockwell Scientific Licensing LLC (Teledyne Technologies Incorporated)
• Inventors: Chien, Charles
• Primary Examiner(s): Fan, Chieh M.
• Application Number:
  US10/055,261
• Publication Number:
  US 20020176482A1
• Time in Patent Office: 1,090 Days
• Field of Search: 375/130, 375/140, 375/141, 375/219, 375/220, 375/222, 375/224, 375/227, 375/229, 375/233, 375/262, 375/267, 375/285, 375/295, 375/296, 375/299, 375/316, 375/341, 375/346, 375/347, 375/348, 375/349, 455/418, 455/63.1, 455/296, 714/774
• US Class Current: 375/224
• CPC Class Codes: H04L 1/0002 by adapting the transmission rate
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 25/0202 Channel estimation

Abstract

The invention monitors a communication channel and estimates its characteristics from time to time, thus providing a dynamic estimate of channel characteristics. Based on the channel characteristics, a control processor calculates a preferred configuration of digital (and optionally, analog) signal processing to best manage the available energy for the present channel characteristics. The selected configuration is then down-loaded into communication modules stored in extra memory during runtime. The communication modules preferably include a one or more of: a reconfigurable forward error correcting codec (with adjustable code lengths and a plurality of code choices); a reconfigurable interleaver with adjustable depth; a decision feedback equalizer (DFE) with a reconfigurable number of taps; maximum likelihood sequence estimator with an adjustable number of states; a frequency hopping coder with an adjustable number of hops or hop rate; and a direct-sequence (or direct sequence spread spectrum) codec with an adjustable number of chips per bit.

Claims

1. A method of adaptively reconfiguring a radio architecture for power efficient or adaptive communications based on communication channel conditions, suitable for use in a reconfigurable radio which allows control of reconfigurable digital signal processing blocks with adjustable parameters, comprising the steps of:

estimating a signal to noise ratio (SNR) and signal-to-interference ration (SIR) based on a channel monitor;

estimating a channel impulse response;

based on the estimate of the channel impulse response, setting parameters of the reconfigurable digital signal processing blocks to mitigate frequency selective fading, wherein said step of setting parameters of the reconfigurable digital signal processing blocks comprises;

determining a delay spread from said channel impulse response by setting a system adjustable threshold over which signal power is not considered in determining a time dispersion of a signal; and

setting the number of taps in a decision feedback equalizer (DFE) to the length of the delay spread normalized to a symbol rate; and

based on the estimates of SIR and SNR, setting additional parameters of the reconfigurable digital signal processing blocks to mitigate interference, noise and time selective fading.

2. The method of claim 1, wherein said step of setting parameters of the reconfigurable digital signal processing blocks comprises:

adjusting the number of states of a maximum likelihood sequence equalizer with a reconfigurable number of states.

3. The method of claim 1, wherein said step of setting parameters of the reconfigurable digital signal processing blocks further comprises:

setting the number of fingers in a rake receiver.

4. The method of claim 1, wherein said step of setting additional parameters of the reconfigurable digital signal processing blocks comprises:

based on the estimated SIR and SNR, setting the code rate of a forward-error correction codec.

5. The method of claim 1, wherein said step of setting additional parameters of the reconfigurable digital signal processing blocks comprises reconfiguring a forward error correction codec.

6. The method of claim 5, wherein said forward error correction codec is reconfigurable to enabled or disabled states.

7. The method of claim 5, wherein said forward error correction codec is configurable to more than one code type.

8. The method of claim 1, wherein said step of setting additional parameters of the reconfigurable digital signal processing blocks further comprises:

setting the depth of an interleaver with a reconfigurable depth.

9. The method of claim 1, wherein said step of setting additional parameters of the reconfigurable digital signal processing blocks comprises reconfiguring a frequency hopping module with reconfigurable number of hops and hopping rate.

10. The method of claim 1, wherein said step of setting additional parameters of the reconfigurable digital signal processing blocks further comprises:

reconfiguring the number of chips per bit of a reconfigurable direct sequencing spread spectrum processing module.

11. The method of claim 1, wherein said steps of reconfiguring setting the parameters and setting the additional parameters of the reconfigurable signal processing blocks comprise programming a field programmable gate array (FPGA) circuit.

12. A digital radio capable of adaptively reconfiguring in response to changes in the characteristics of a communication channel, comprising:

a channel monitor which produces estimates of the communication channel'"'"'s signal-to-noise ratio (SNR), signal-to-interference ratio (SIR), and channel impulse response characteristics;

a programmable processor arranged to receive estimates from said channel monitor, and compute a preferred signal processing configuration based upon said estimates;

at least one reconfigurable digital signal processing module, including at least one decision feedback equalizer (DFE) with an adjustable number of taps, arranged to receive commands from said programmable processor and to reconfigure in response to said commands;

said processor further arranged to;

determine a delay spread from said channel impulse response estimate by setting a system adjustable threshold over which signal power is not considered in determining a time dispersion of a signal; and

set the number of taps in said at least one DFE to the length of the delay spread normalized to a symbol rate; and

a radio transceiver, with inputs from said reconfigurable signal processing module and outputs to said channel monitor, for sending and receiving radio signals.

13. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises a forward error correction (FEC) codec.

14. The digital radio of claim 13, wherein said FEC codec is reconfigurable to enabled or disabled states in response to commands from said programmable processor.

15. The digital radio of claim 14, wherein said FEC codec is further reconfigurable to any of a plurality of codes, in response to commands from said processor.

16. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises a maximum likelihood sequence equalizer with a reconfigurable number of states.

17. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises an interleaver with a reconfigurable depth.

18. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises a frequency hopping module with reconfigurable number of hops and hopping rate.

19. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises a reconfigurable direct sequencing spread spectrum processing module with an adjustable number of chips per bit.

20. The digital radio of claim 12, wherein said reconfigurable digital signal processing module comprises a field programmable gate array circuit, interfaced to said processor and arranged to reconfigure in response to commands from said processor.