Wireless communication apparatus processing intermittent data

• US 6,807,235 B2
• Filed: 03/01/2001
• Issued: 10/19/2004
• Est. Priority Date: 02/09/2001
• Status: Expired due to Fees

• Current Assignee: Maxell, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yano, Takashi, Suzuki, May
• Primary Examiner(s): Tse, Young T.
• Application Number:
  US09/795,110
• Publication Number:
  US 20020111199A1
• Time in Patent Office: 1,328 Days
• Field of Search: 375/259, 375/377, 370/311, 370/328, 370/337, 370/347, 370/349, 340/3.1, 340/3.21, 455/522, 455/574, 713/322
• US Class Current: 375/259
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

In order to effectively reduce power consumption of a terminal in a wireless communication apparatus upon packet communication, the wireless communication apparatus has a plurality of signal processing blocks having different signal processing periods; a buffer memory which links the signal processing blocks; and a clock control part which supplies or suspends a clock signal to each block. Each of the signal processing blocks watches whether or not there is data to be processed in the subsequent signal processing block. Based on the watched result, the clock control part controls an operation to supply or suspend the clock signal to the subsequent signal processing block.

Claims

1. A wireless communication apparatus having a wireless processing part for processing a wireless signal including intermittent data and a base band signal processing part for receiving/transmitting said intermittent data to/from said wireless processing part, wherein said base band signal processing part comprises:

a plurality of signal processing blocks having different signal processing periods;

a buffer memory which is provided between said plurality of signal processing blocks;

a clock control part which supplies a clock signal to each of said plurality of signal processing blocks and said buffer memory;

a power source control part which supplies a power source to each of said plurality of signal processing parts and said buffer memory; and

a control engine which controls said plurality of signal processing blocks, said buffer memory, said clock control part, and said power source control part, and

at least one of said plurality of signal processing blocks has means for watching which watches whether or not there is data to be processed in the subsequent signal processing block having the different signal processing period, and

said control engine also controls said clock control part to supply or suspend the clock signal to said subsequent signal processing block based on a watched result of said means for watching.

2. A wireless communication apparatus according to claim 1, wherein said control engine further controls said power source control part to supply the power source to be supplied to said subsequent signal processing block based on said watched result.

3. A wireless communication apparatus according to claim 1, wherein said intermittent data comprises a signal with a signal format including a periodic control data portion and a user data portion, and is a signal that a control signal is periodically transmitted when there is not said user data portion, and

said at least one of signal processing blocks watches the existence of said user data portion and, when there is not said user data portion as the watched result, said control engine controls said clock control part to supply or suspend the clock signal to said at least one of signal processing blocks over a period in which said user data portion is to be processed.

4. A wireless communication apparatus according to claim 3, wherein said control engine further has means for controlling said power source control part to control the power source to be supplied to said subsequent signal processing block based on said watched result.

5. A wireless communication apparatus according to claim 1, wherein said intermittent data comprises a signal with a signal format including a periodic control data portion and a user data portion, is a signal that a control signal is periodically transmitted when there is not user data portion, and is a signal to suspend said periodic control data portion when there is not said user data portion sequentially a predetermined times or more, and

said control engine controls said clock control part to supply or suspend the clock signal for a period in which the control signal is to be processed to at least one of said plurality of signal processing blocks based on said watched result.

6. A wireless communication apparatus according to claim 5, wherein said control engine further controls said power source part to control the power source to be supplied to said subsequent signal processing block based on said watched result.

7. A large scale integrated circuit comprising:

a plurality of signal processing blocks having different signal processing periods;

a buffer memory which is provided between said plurality of signal processing blocks;

a clock control part which supplies a clock signal to each of said plurality of signal processing blocks and said buffer memory;

a power source control part which supplies a power source to each of said plurality of signal processing blocks and said buffer memory; and

a control engine which controls said plurality of signal processing blocks, said buffer memory, said clock control part, and said power source control part, wherein

at least one of said plurality of signal processing blocks has means for watching which watches whether or not there is data to be processed in the subsequent signal processing block having the different processing period, and said control engine has means for controlling said clock control part to supply or suspend the clock signal to said subsequent signal processing block based on a watched result of said means for watching.

8. A large scale integrated circuit according to claim 7, wherein said plurality of signal processing blocks having the different signal processing periods has:

a signal processing block which processes data based on a symbol unit;

a signal processing block which processes data based on a slot unit; and

a signal processing block which processes data based on a frame unit.