Method for measuring PLL lock time

• US 6,807,498 B2
• Filed: 07/16/2002
• Issued: 10/19/2004
• Est. Priority Date: 02/22/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Premy, Amit Kumar
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US10/195,906
• Publication Number:
  US 20030163267A1
• Time in Patent Office: 826 Days
• Field of Search: 702/79, 702/69, 702/76, 702/89, 702/107, 331/44, 324/521
• US Class Current: 702/79
• CPC Class Codes: G01R 31/2824 testing of oscillators or resonators

Abstract

A method of measuring the PLL lock time includes deriving the PLL frequency-settling function by demodulation and envelope extraction in the time domain. The PLL lock time can then be calculated from this function. Using this PLL lock time measurement method provides for very good frequency and time accuracy. Also, since for demodulation, the settled signal is used for multiplication, ATE synchronization is not required. Furthermore, since all the processing is done in the time domain, calculation times are reduced, making the process suitable for ATE environments.

Claims

1. A method for measuring the lock time of a phase lock loop (PLL) that provides an output signal, comprising the steps of:

(a) capturing the PLL output signal over a predetermined amount of time;

(b) performing amplitude normalization on the captured PLL output signal;

(c) dividing the captured waveform into two waveforms, y1 and y2;

(d) multiplying the two waveforms y1 and y2 together and by a predetermined factor in order to derive a waveform, y3;

(e) deriving the envelope of y3 in order to generate an envelope waveform y4;

(f) performing an arccosine operation to the envelope waveform y4 in order to generate a waveform y5;

(g) differentiating waveform y5 with respect to time in order to generate a waveform y6;

(h) dividing waveform y6 by a predetermined amount in order to generate a waveform y7; and

(i) measuring the lock time of the PLL using waveform y7.

2. The method as defined in claim 1, wherein step (b) comprises the substeps of

(b1) determining the amplitude and mean from a portion of the captured output signal; and

(b2) subtracting the mean determined in step (b1) from the PLL output signal captured in step (a); and

(b3) normalizing the result from step (b2) by dividing the result of step (b2) by the amplitude.

3. A method as defined in claim 2, wherein the portion of the output signal that the mean and amplitud determined in step (b1) are derived from a latter portion of the PLL output signal captured in step (a) after the PLL output signal has settled.

4. A method as defined in claim 1, wherein in step (c) the waveforms y1 and y2 are divided into equal time length waveforms.

5. A method as defined in claim 1. wherein the predetermined factor in step (d) is equal to two.

6. A method as defined in claim 1, wherein the predetermined amount in step (h) is 2π

.

7. A method as defined in claim 1, wherein waveform y1 can be represented as y1(t)=cos(2π

f₀t+g(t)+φ

₁), for 0=<

t<

T/2, and waveform y2 can be represented as y2(t)=cos(2π

f₀t+φ

₂), for T/2=<

t<

T, where T is the amount of time the PLL output signal is captured, f₀=locked frequency of the PLL, g(t)=phase modulation function (in radians), which becomes zero when the PLL is locked, and φ

₁=initial phase of waveform y1, and φ

₂=initial phase of waveform y2.

8. A method as defined in claim 7, where y3 contains a high frequency component, z1=cos(4π

f₀t+g(t)+φ

₁+φ

₂) and a low frequency component z2=[cos (g(t)+φ

₁−

φ

₂)], and a time interval Δ

T is considered, such that T=NΔ

T, Δ

T is chosen such that Δ

T contains multiple cycles of z1, and the value of z2 is relatively constant in this time interval, and in step (e) waveform y4 is equal to;

y4 (nΔ

T)=cos(g(nΔ

T)+φ

₁−

φ

₂) for 0=<

n<

N.

9. A method as defined in claim 8, wherein in step (f), waveform y5 is equal to y5 (nΔ

T)=cos<sup>−

1</sup>[y4(nΔ

T)]=g(nΔ

T)+φ

₁−

φ

₂ for 0=<

n<

N, and where waveform y5 represents the phase modulation function.

10. A method as defined in claim 9, wherein in step (g), waveform y6 is equal to y6 (nΔ

T)=(y5(nΔ

T)−

y5((n−

1)Δ

T))/Δ

T for 1=<

N;

where waveform y6 represents d/dt(g(t)), and is the frequency modulation term (in radians/sec) that is of interest.

11. A method as defined in claim 10, wherein waveform y7 is equal to y7(nΔ

T)=y6(nΔ

T)/2 for 1=<

n<

N, where y7 gives the frequency variation with respect to f₀ (in Hz) versus time.

12. A method as defined in claim 1, wherein in step (I) the PLL lock time is calculated from waveform y7 by determining the time after which the frequency variation relative to f₀ is within the required limits.

13. A method for measuring the lock time of a phase lock loop (PLL) that provides an output signal, comprising the steps of:

(a) capturing the PLL output signal over a predetermined period of time;

(b) deriving a PLL frequency-settling function from the captured PLL output signal; and

(c) determining the PLL lock time from the PLL frequency-settling function;

wherein in step (b) the PLL frequency-settling function is derived by performing demodulation and envelope extraction of the captured PLL output signal in the time domain.

14. A method as defined in claim 13, wherein step (a) is performed using a digitizer.