Apparatus for testing I/O ports of a computer motherboard

• US 6,807,504 B2
• Filed: 11/21/2002
• Issued: 10/19/2004
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Huang, Chih-Wei, Chen, Zhiguo
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US10/300,737
• Publication Number:
  US 20040102917A1
• Time in Patent Office: 698 Days
• Field of Search: 702/57, 702/64, 702/65, 702/79, 702/80, 702/89, 702/117-119, 710/302, 710/301, 714/8, 714/25, 714/732, 326/30, 326/31, 716/228, 712/228
• US Class Current: 702/118
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units

Abstract

An apparatus for testing I/O ports of a computer motherboard. A non-volatile memory on a computer motherboard under test stores a test code instead of a normal BIOS code to initialize the computer motherboard under test and test its I/O ports. The computer motherboard under test is booted from the test code. For the I/O ports to be tested, a CPU on the computer motherboard under test executes test routines in the test code. The apparatus of the invention is connected to the computer motherboard under test so as to cooperate with the test routines in testing the I/O ports. Furthermore, the inventive apparatus includes connectors and test circuits for establishing electrical connections with corresponding pins of the I/O ports to be tested and checking each pin with the test routines.

Claims

1. An apparatus for testing I/O ports of a computer motherboard operationally under control of a test code, comprising:

a circuit board;

a first connector electrically connected to the circuit board, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of a parallel port of the computer motherboard;

a first test circuit coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector;

a second connector electrically connected to the circuit board, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of a USB port of the computer motherboard; and

a second test circuit coupled to the second connector, comprising;

a first resistor connected between a first voltage source and one of the USB interface differential data pins;

a second resistor connected between a second voltage source and the other USB interface differential data pin; and

a third resistor connected between the pair of USB interface differential data pins;

wherein the first, the second and the third resistors are connected in series.

2. The apparatus as recited in claim 1 wherein the logic device of the first test circuit comprises:

a first NAND gate coupled to logically operate a portion of the parallel interface data pins on the first connector and to provide a first logic signal to a first pin of the portion of the parallel interface status pins on the first connector;

a second NAND gate coupled to logically operate the other portion of the parallel interface data pins on the first connector and to provide a second logic signal to a second pin of the portion of the parallel interface status pins on the first connector; and

a third NAND gate coupled to logically operate the control pins on the first connector and to provide a third logic signal to a third pin of the portion of the parallel interface status pins on the first connector;

wherein the first, the second and the third logic signals constitute the set of logic signals provided to the portion of the parallel interface status pins.

3. The apparatus as recited in claim 2 wherein the first test circuit electrically couples a fourth and fifth pin of the parallel interface status pins on the first connector, except the portion of the parallel interface status pins, to the second voltage source.

4. The apparatus as recited in claim 3 wherein the first pin of the portion of the parallel interface status pins is a PAPER END status pin on the first connector, the second pin of the portion of the parallel interface status pins is a SELECT status pin on the first connector, the third pin of the portion of the parallel interface status pins is an ERROR status pin on the first connector, the fourth pin of the parallel interface status pins is an ACK status pin on the first connector, and the fifth pin of the parallel interface status pins is a BUSY status pin on the first connector.

5. The apparatus as recited in claim 4 wherein the first test circuit electrically couples the ACK and the BUSY status pins on the first connector to ground.

6. The apparatus as recited in claim 2 wherein the parallel interface control pins include a SLIN control pin on the first connector, an INIT control pin on the first connector, an AUTO FEED control pin on the first connector, and a STROBE control pin on the first connector.

7. The apparatus as recited in claim 1 wherein the first voltage source is a power supply source and the second voltage source is ground.

8. The apparatus as recited in claim 1 further comprising:

a third connector electrically connected to the circuit board, including a plurality of game interface pins, for establishing electrical connections with corresponding pins of a game port of the computer motherboard; and

a third test circuit, coupled to the third connector, for coupling a portion of the game interface pins to the first voltage source by way of pull-up resistors and coupling the other portion of the game interface pins to the second voltage source.

9. The apparatus as recited in claim 8 wherein the game interface pins on the third connector include a first button pin, a second button pin, an X-axis position pin and a Y-axis position pin.

10. The apparatus as recited in claim 9 wherein the first and the second button pins are coupled to the first voltage source through the pull-up resistors, and the X-axis and Y-axis position pins are coupled to the second voltage source.

11. The apparatus as recited in claim 10 wherein the first voltage source is a power supply source and the second voltage source is ground.

12. The apparatus as recited in claim 1 further comprising:

a fourth connector electrically connected to the circuit board, having a first serial interface control pin coupled to a first and second serial interface status pins together to form a first loop-back connection, a second serial interface control pin coupled to a third and fourth serial interface status pins together to form a second loop-back connection, and a serial data output pin coupled to a serial data input pin to form a third loop-back connection, for establishing electrical connections with corresponding pins of a serial port of the computer motherboard.

13. The apparatus as recited in claim 12 wherein the first serial interface control pin is a DTR pin on the fourth connector and the second serial interface control pin is a RTS pin on the fourth connector.

14. The apparatus as recited in claim 12 wherein the first serial interface status pin is a DCD pin on the fourth connector, the second serial interface status pin is a DSR pin on the fourth connector, the third serial interface status pin is a CTS pin on the fourth connector, and the fourth serial interface status pin is a RI pin on the fourth connector.

15. The apparatus as recited in claim 12 wherein the serial data output pin is a TXD pin on the fourth connector and the serial data input pin is a RXD pin on the fourth connector.

16. The apparatus as recited in claim 1 further comprising:

a fifth connector electrically connected to the circuit board, having a pair of transmit pins correspondingly coupled to a pair of receive pins to form a pair of loop-back connections, for establishing electrical connections with corresponding pins of a network port of the computer motherboard.

17. The apparatus as recited in claim 1 further comprising:

a sixth connector electrically connected to the circuit board, having an audio interface pin, for establishing an electrical connection with a corresponding pin of an audio port of the computer motherboard; and

an oscillator, coupled to the audio interface pin, for generating a test signal to the first audio interface pin.

18. The apparatus as recited in claim 17 wherein the first input output pin is a microphone pin of the audio port, the first and the second output pins form a pair of stereo output pins of the audio port, and the second and the third audio input pins form a pair of stereo input pins of the audio port.

19. The apparatus as recited in claim 1 further comprising:

a seventh connector electrically connected to the circuit board, having a keyboard interface clock pin coupled to a keyboard interface data pin to form a loop-back connection, for establishing electrical connections with corresponding pins of a keyboard port of the computer motherboard.

20. The apparatus as recited in claim 1 further comprising:

an eighth connector electrically connected to the circuit board, having a PS/2 interface clock pin coupled to a PS/2 interface data pin to form a loop-back connection, for establishing electrical connections with corresponding pins of a PS/2 mouse port of the computer motherboard.

47. An apparatus as recited in claim 1, wherein the motherboard comprises a CPU and a memory, and wherein the test code is stored in the memory during the testing and executed by the CPU, the execution of the test code causing the motherboard to at least one of send signals to and receive signals from the connectors during the testing.

21. An apparatus for testing I/O ports of a computer motherboard comprising:

a computer motherboard under test comprising;

a plurality of I/O ports including a parallel port and a USB port;

a non-volatile memory for storing a test code, instead of a basic input-output system (BIOS) code, to initialize the computer motherboard under test and test the I/O ports; and

a central processing unit (CPU) booting from the test code in the non-volatile memory for executing the test code to test the I/O ports of the computer motherboard under test;

a first connector, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of the parallel port of the computer motherboard under test;

a first test circuit, coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector;

a second connector, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of the USB port of the computer motherboard under test; and

a second test circuit, coupled to the second connector, comprising;

a first resistor connected between a first voltage source and one of the USB interface differential data pins;

a second resistor connected between a second voltage source and the other USB interface differential data pin; and

a third resistor connected between the pair of USB interface differential data pins;

wherein the first, the second and the third resistors are connected in series.

22. The apparatus as recited in claim 21 wherein the logic device of the first test circuit comprises:

a first NAND gate coupled to logically operate a portion of the parallel interface data pins on the first connector and to provide a first logic signal to a first pin of the portion of the parallel interface status pins on the first connector;

a second NAND gate coupled to logically operate the other portion of the parallel interface data pins on the first connector and to provide a second logic signal to a second pin of the portion of the parallel interface status pins on the first connector; and

a third NAND gate coupled to logically operate the control pins on the first connector and to provide a third logic signal to a third pin of the portion of the parallel interface status pins on the first connector;

wherein the first, the second and the third logic signals constitute the set of logic signals provided to the portion of the parallel interface status pins.

23. The apparatus as recited in claim 22 wherein the first test circuit electrically couples a fourth and fifth pin of the parallel interface status pins on the first connector, except the portion of the parallel interface status pins, to the second voltage source.

24. The apparatus as recited in claim 23 wherein the first pin of the portion of the parallel interface status pins is a PAPER END status pin on the first connector, the second pin of the portion of the parallel interface status pins is a SELECT status pin on the first connector, the third pin of the portion of the parallel interface status pins is an ERROR status pin on the first connector, the fourth pin of the parallel interface status pins is an ACK status pin on the first connector, and the fifth pin of the parallel interface status pins is a BUSY status pin on the first connector.

25. The apparatus as recited in claim 24 wherein the first test circuit electrically couples the ACK and the BUSY status pins on the first connector to ground.

26. The apparatus as recited in claim 22 wherein the parallel interface control pins include a SLIN control pin on the first connector, an INIT control pin on the first connector, an AUTO FEED control pin on the first connector, and a STROBE control pin on the first connector.

27. The apparatus as recited in claim 21 wherein the first voltage source is a power supply source and the second voltage source is ground.

28. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise a game port.

29. The apparatus as recited in claim 28 further comprising:

a third connector, including a plurality of game interface pins, for establishing electrical connections with corresponding pins of the game port of the computer motherboard under test; and

a third test circuit, coupled to the third connector, for coupling a portion of the game interface pins to the first voltage source by way of pull-up resistors and coupling the other portion of the game interface pins to the second voltage source.

30. The apparatus as recited in claim 29 wherein the game interface pins on the third connector include a first button pin, a second button pin, an X-axis position pin and a Y-axis position pin.

31. The apparatus as recited in claim 30 wherein the first and the second button pins are coupled to the first voltage source through the pull-up resistors, and the X-axis and Y-axis position pins are coupled to the second voltage source.

32. The apparatus as recited in claim 31 wherein the first voltage source is a power supply source and the second voltage source is ground.

33. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise a serial port.

34. The apparatus as recited in claim 33 further comprising:

a fourth connector having a first serial interface control pin coupled to first and second serial interface status pins together to form a first loop-back connection, a second serial interface control pin coupled to third and fourth serial interface status pins together to form a second loop-back connection, and a serial data output pin coupled to a serial data input pin to form a third loop-back connection, for establishing electrical connections with corresponding pins of the serial port of the computer motherboard under test.

35. The apparatus as recited in claim 34 wherein the first serial interface control pin is a DTR pin on the fourth connector and the second serial interface control pin is a RTS pin on the fourth connector.

36. The apparatus as recited in claim 34 wherein the first serial interface status pin is a DCD pin on the fourth connector, the second serial interface status pin is a DSR pin on the fourth connector, the third serial interface status pin is a CTS pin on the fourth connector, and the fourth serial interface status pin is a RI pin on the fourth connector.

37. The apparatus as recited in claim 34 wherein the serial data output pin is a TXD pin on the fourth connector and the serial data input pin is a RXD pin on the fourth connector.

38. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise a network port.

39. The apparatus as recited in claim 38 further comprising:

a fifth connector having a pair of transmit pins correspondingly coupled to a pair of receive pins to form a pair of loop-back connections, for establishing electrical connections with corresponding pins of the network port of the computer motherboard under test.

40. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise an audio port.

41. The apparatus as recited in claim 40 further comprising:

a sixth connector having an audio interface pin, for establishing an electrical connection with a corresponding pin of the audio port of the computer motherboard under test; and

an oscillator, coupled to the audio interface pin, for generating a test signal to the audio interface pin.

42. The apparatus as recited in claim 41 wherein the first input output pin is a microphone pin of the audio port, the first and the second output pins form a pair of stereo output pins of the audio port, and the second and the third audio input pins form a pair of stereo input pins of the audio port.

43. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise a keyboard port.

44. The apparatus as recited in claim 43 further comprising:

a seventh connector having a keyboard interface clock pin coupled to a keyboard interface data pin to form a loop-back connection, for establishing electrical connections with corresponding pins of the keyboard port of the computer motherboard under test.

45. The apparatus as recited in claim 21 wherein the I/O ports of the computer motherboard under test further comprise a PS/2 mouse port.

46. The apparatus as recited in claim 45 further comprising:

an eighth connector having a PS/2 interface clock pin coupled to a PS/2 interface data pin to form a loop-back connection, for establishing electrical connections with corresponding pins of the PS/2 mouse port of the computer motherboard under test.