Disconnecting a device on a cache line boundary in response to a write command

• US 6,807,590 B1
• Filed: 04/04/2000
• Issued: 10/19/2004
• Est. Priority Date: 04/04/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Carlson, Jeff M., Callison, Ryan A.
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/542,157
• Time in Patent Office: 1,659 Days
• Field of Search: 710/57, 710/62, 710/129, 709/25, 713/224
• US Class Current: 710/57
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/306 In system interconnect, e.g. between two buses

Abstract

Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.

Claims

1. A method for processing write commands from a device in a computer system, comprising the steps of:

detecting a write command from a computer device, thereby initiating a write operation;

receiving data in a buffer in response to the write command;

monitoring the status of the buffer to determine the amount of data in the buffer; and

disconnecting the computer device to terminate the write operation when the buffer reaches a buffer full status such that the write operation is terminated when the data is aligned with a cache line boundary.

2. The method of claim 1, the disconnecting step further comprising the steps of:

configuring the buffer full status to equal a capacity of the buffer when unused buffer capacity equals a multiple of a cache line of data; and

configuring the buffer full status to equal a level of buffer capacity less than a total buffer capacity.

3. The method of claim 2, wherein the level of buffer capacity less than the total buffer capacity is equal to an additional cache line of data calculated from the last data written to the buffer.

4. The method of claim 2, wherein calculation of the level of buffer capacity less than the total buffer capacity comprises the steps of:

calculating an adjusted buffer capacity by rounding down the buffer capacity to a multiple of a cache line size; and

substracting from the adjusted buffer capacity a portion of a starting write address.

5. The method of claim 1, the monitoring step further comprising the steps of:

calculating an amount of unused buffer capacity by substracting an absolute difference between a buffer reading address and a buffer writing address from the total buffer capacity.

6. A computer bridge device for performing computer write operations between multiple systems, comprising:

a receiving device for receiving write commands from a system device;

a buffer coupled to the receiving device, the buffer having a buffer capacity; and

a means for disconnecting the receiving device from the system device to terminate a write operation when the buffer approaches a buffer full status such that the write operation is terminated when data in the buffer is aligned with a cache line boundary.

7. The computer bridge device of claim 6, further comprising:

a means for measuring a status of the buffer to determine an amount of data in the buffer.

8. The computer bridge device of claim 6, further comprising:

a means for detecting a cache line size.

9. The computer bridge device of claim 8, further comprising:

a means for determining if unused capacity of the buffer is a multiple of the cache line size.

10. The computer bridge device of claim 8, further comprising:

a means for adjusting the buffer full status such that an unused capacity of the buffer is a multiple of the cache line size.

11. A computer system for performing computer write operations, comprising:

a system device; and

a bridge coupled to the system device, the bridge comprising;

a receiving device for receiving write commands from a system device;

a buffer coupled to the receiving device, the buffer having a buffer capacity;

a means for disconnecting the receiving device from the system device to terminate a write operation when the buffer approaches a buffer full status such that the write operation is terminated when data in the buffer is aligned with a cache line boundary.

12. The computer system of claim 11, the bridge, further comprising:

a means for measuring a status of the buffer to determine an amount of data in the buffer.

13. The computer system of claim 11, the bridge, further comprising:

a means for detecting a cache line size.

14. The computer system of claim 13, the bridge, further comprising:

a means for determining if unused capacity of the buffer is a multiple of the cache line size.

15. The computer system of claim 13, the bridge, further comprising:

a means for adjusting the buffer full status such that an unused capacity of the buffer is a multiple of the cache line size.

16. A method for performing computer write operations, the method comprising the steps of:

detecting a write command, thereby initiating a write operation;

receiving data in response to the write command;

calculating an amount of received data responsive to the write command for disconnection of the write operation when the amount of the received date is aligned with a cache line boundary.

17. The method of claim 16, wherein the calculation step is performed by an alignment engine, the alignment engine causing a write command initiating device to be disconnected from a receiving data buffer when the received data is aligned with a cache line boundary.

18. The method of claim 16, the step of calculating the amount of received data, comprising the steps of:

adjusting an amount of available capacity to receive additional data;

calculating a start location within a cache-line from a starting address of the write command; and

calculating a maximum write transfer value by subtracting the start location from the adjusted amount of available capacity.

19. The method of claim 18, wherein the step of adjusting an amount of available capacity comprises calculating an adjusted free space value from an actual free space value representing an actual capacity of the receiving buffer.