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Integrated circuit device having double data rate capability

DC
  • US 6,807,598 B2
  • Filed: 01/22/2002
  • Issued: 10/19/2004
  • Est. Priority Date: 04/18/1990
  • Status: Expired due to Fees
First Claim
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1. A synchronous integrated circuit memory device including an array of memory cells, wherein the memory device comprises:

  • a clock receiver to receive an external clock signal;

    a plurality of output drivers to output data, wherein;

    a first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal; and

    a second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal; and

    a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.

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