Method and apparatus for using smart memories in computing

• US 6,807,614 B2
• Filed: 03/14/2002
• Issued: 10/19/2004
• Est. Priority Date: 07/19/2001
• Status: Active Grant

• Current Assignee: Stripe, Inc.
• Original Assignee: Shine C. Chung
• Inventors: Chung, Shine C.
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): Truong, Bao Q.
• Application Number:
  US10/099,440
• Publication Number:
  US 20030018868A1
• Time in Patent Office: 950 Days
• Field of Search: 709/107, 709/108, 711/168
• US Class Current: 711/168
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/3576 Multiple memory zones on card
• CPC Class Codes: G07F 7/084 Additional components relating to data transfer and storing, e.g. error detection, self-diagnosis
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.

Claims

1. A smart memory computing system to process data in parallel, said smart memory system comprising:

a central processing unit;

a main memory unit that provides data storage for said central processing unit;

a smart memory unit to not only store data for said central processing unit but also to process data therein;

a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system; and

a trigger mechanism for said central processing unit to initiate processing of a processing batch by said smart memory unit.

2. A smart memory computing system as recited in claim 1, wherein said smart memory unit operates as a coprocessor for said central processing unit.

3. A smart memory computing system as recited in claim 1, wherein said smart memory computing system further comprises:

a chip set to facilitate said central processing unit in accessing said main memory unit and said smart memory unit therethrough.

4. A smart memory computing system as recited in claim 1, wherein said central processing unit can comprises at least one of an Arithmetic and Logic Unit (ALU), a floating-point processor, a single-instruction-multiple-data execution unit, and a special function processor.

5. A smart memory computing system as recited in claim 1, wherein said smart memory computing system further comprises:

A set of mechanisms for said central processing unit to interact with said smart memory unit.

6. A smart memory computing system as recited in claim 1, wherein said smart memory computing system further comprising:

a notification mechanism for said smart memory unit to notify said central processing unit of completion of the processing batch.

7. A smart memory computing system as recited in claim 1, wherein said smart memory computing system further comprising:

an interrupt controller within or coupled to said smart memory unit, said interrupt controller for interrupting the processing batch by said smart memory unit.

8. A smart memory computing system as recited in claim 7, wherein said smart memory computing system further comprising:

a notification mechanism for said smart memory unit to notify said central processing unit of completion of a processing batch.

9. A smart memory computing system as recited in claim 7, wherein said smart memory computing system further comprising:

a bus operatively connecting said smart memory unit to at least one of said main memory unit and said central processing unit.

10. A smart memory computing system as recited in claim 9, wherein said smart memory unit comprises a first port coupled to said bus and a second port for coupled to an external device.

11. A smart memory computing system as recited in claim 9, wherein said bus is one of a memory bus, an I/O bus or a graphics bus.

12. A smart memory computing system as recited in claim 1, wherein said smart memory unit comprises a first smart memory integrated circuit and a second smart memory integrated circuit.

13. A smart memory computing system as recited in claim 1, wherein said smart memory unit comprises at least one smart memory integrated circuit.

14. A smart memory computing system as recited in claim 13, wherein said smart memory integrated circuit comprises:

an instruction memory;

a plurality of data memory blocks that store data for general storage or buffering as well as for processing;

an input cross-bar switch coupled to said data memory blocks;

a plurality of execution units coupled to said input cross-bar switch and thus to said data memory blocks, said execution units execute instructions stored in said instruction memory;

an output cross-bar switch coupled to said execution units;

a plurality of control and status registers;

control logic;

a plurality of configuration registers; and

bus interface logic.

15. A smart memory computing system as recited in claim 14, wherein said bus interface logic is responsible for requesting bus ownership, accepting triggering or interrupt signals, synchronizing within smart memory system, or producing interrupt signal.

16. A smart memory computing system to process data in parallel, said smart memory system comprising:

a central processing unit;

a main memory unit that provides data storage for said central processing unit;

a smart memory unit to not only store data for said central processing unit but also to process data therein;

a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system; and

a stall mechanism for stalling execution by at least part of said smart memory unit.

17. A smart memory computing system as recited in claim 16, wherein the part of said smart memory system activates said stall mechanism.

18. A smart memory computing system to process data in parallel, said smart memory system comprising:

a central processing unit;

a main memory unit that provides data storage for said central processing unit;

a smart memory unit to not only store data for said central processing unit but also to process data therein, wherein said smart memory unit comprises a first smart memory integrated circuit and a second smart memory integrated circuit;

a massive data storage that provide storage for a superset of data stored in said main memory system and in said smart memory system; and

a bus operatively connecting said first and second smart memory integrated circuits to at least one of said main memory unit and said central processing unit.

19. A smart memory computing system as recited in claim 18, wherein said smart memory computing system further comprising:

an interrupt controller within or coupled to said smart memory unit, said interrupt controller for interrupting a processing batch by said smart memory unit.

20. A smart memory computing system as recited in claim 18, wherein said first and second smart memory integrated circuits are able to request usage of said bus for data transfer.

21. A smart memory computing system as recited in claim 20, wherein data can be passed between said first and second smart memory integrated circuits over said bus.

22. A smart memory computing system to process data in parallel, said smart memory system comprising:

a central processing unit;

a main memory unit that provides data storage for said central processing unit;

a smart memory unit to not only store data for said central processing unit but also to process data therein;

a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system;

means for said central processing unit to interact with said smart memory system; and

a trigger mechanism for said central processing unit to initiate processing of a processing batch by said smart memory unit.