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Memory address checking in a proccesor that support both a segmented and a unsegmented address space

  • US 6,807,616 B1
  • Filed: 08/09/2001
  • Issued: 10/19/2004
  • Est. Priority Date: 08/09/2001
  • Status: Active Grant
First Claim
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1. An apparatus for a processor, the apparatus comprising:

  • circuitry configured to perform one or more canonical checks for a data reference and a segment limit check on an effective address of the data reference, wherein a canonical check is a check to ensure, for an address of the data reference, that each address bit that is not included in an implemented address space of the processor is equal to a most significant address bit that is included in the implemented address space; and

    a first circuit coupled to the circuitry and coupled to receive an indication of an operating mode of the processor and an indication of the segment corresponding to the data reference, wherein the first circuit is configured to select, responsive to the operating mode of the processor and the segment, one or more of;

    a first result of the segment limit check and a second result of the one or more canonical checks for generating an exception indication for the data reference.

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