Memory address checking in a proccesor that support both a segmented and a unsegmented address space

• US 6,807,616 B1
• Filed: 08/09/2001
• Issued: 10/19/2004
• Est. Priority Date: 08/09/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Keltcher, Chetana N., McGrath, Kevin J., Haddad, Ramsey W.
• Primary Examiner(s): Verbrugge, Kevin
• Assistant Examiner(s): SONG, JASMINE
• Application Number:
  US09/927,023
• Time in Patent Office: 1,167 Days
• Field of Search: 711/202, 711/203, 711/206, 711/207, 711/208, 711/209, 712/210, 712/244
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

A processor supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used. In the unsegmented address space, a canonical check applies to addresses. In the segmented address space, a segment limit check applies. In some cases, both a segment limit check and a canonical check applies dependent on the segment used (e.g. either user or table segments). An exception circuit selects one or more of the canonical check result(s) and the segment limit check result to generate an exception indication. The selection is dependent on the operating mode and the segment of the data reference. The processor may also perform selective truncation of addresses based on the operating mode and the segment.

Claims

1. An apparatus for a processor, the apparatus comprising:

circuitry configured to perform one or more canonical checks for a data reference and a segment limit check on an effective address of the data reference, wherein a canonical check is a check to ensure, for an address of the data reference, that each address bit that is not included in an implemented address space of the processor is equal to a most significant address bit that is included in the implemented address space; and

a first circuit coupled to the circuitry and coupled to receive an indication of an operating mode of the processor and an indication of the segment corresponding to the data reference, wherein the first circuit is configured to select, responsive to the operating mode of the processor and the segment, one or more of;

a first result of the segment limit check and a second result of the one or more canonical checks for generating an exception indication for the data reference.

2. An apparatus for a processor, the apparatus comprising:

circuitry configured to perform one or more canonical checks for a data reference and a segment limit check on an effective address of the data reference; and

a first circuit coupled to the circuitry and coupled to receive an indication of an operating mode of the processor and an indication of the segment corresponding to the data reference, wherein the first circuit is configured to select, responsive to the operating mode of the processor and the segment, one or more of;

a first result of the segment limit check and a second result of the one or more canonical checks for generating an exception indication for the data reference, wherein the one or more canonical checks include a first canonical check on the effective address and a second canonical check on a linear address of the data reference, and wherein the second result is the result of the first canonical check, and a third result is the result of the second canonical check, and wherein the first circuit is further configured to select the third result for generating the exception indication responsive to the operating mode and the segment.

3. The apparatus as recited in claim 2, wherein the first circuit is configured to select the first result and not select the second result and the third result if the operating mode specifies a segmented address space in which a linear address size is less than or equal to 32 bits.

4. The apparatus as recited in claim 2, wherein the first circuit is configured to select the first result if the operating mode specifies a segmented address space in which a linear address size in at least some segments is greater than 32 bits.

5. The apparatus as recited in claim 4 wherein the first circuit is further configured to select the third result and not select the second result if the segment is a table segment.

6. The apparatus as recited in claim 2 wherein the first circuit is configured to select the third result if the operating mode specifies an unsegmented address space.

7. The apparatus as recited in claim 6 wherein the first circuit is further configured to select the second result and not select the first result if the segment is a user segment.

8. The apparatus as recited in claim 6 wherein the first circuit is further configured to select the first result and not select the second result if the segment is a table segment.

9. The apparatus as recited in claim 2 wherein the circuitry comprises a second circuit located in an address generation unit configured to generate the effective address, wherein the second circuit is configured to generate the second result and to transmit the indication to the first circuit, and wherein the first circuit is located in a load/store unit.

10. An apparatus for a processor comprising:

a circuit configured to output an address of a data reference, the circuit coupled to receive a control input and configured to output the address either truncated to a predetermined number of bits or not truncated dependent on the control input; and

a control circuit configured to generate the control input responsive to a segment of the data reference and an operating mode of the processor, wherein the control circuit is configured to generate the control input to truncate if the operating mode specifies a segmented address space in which a linear address size in at least some segments is greater than 32 bits and the segment is a user segment.

11. The apparatus as recited in claim 10 wherein the control circuit is configured to generate the control input to truncate if the operating mode specifies a segmented address space in which a linear address size is less than or equal to 32 bits.

12. The apparatus as recited in claim 10 wherein the control circuit is configured to generate the control input not to truncate if the operating mode specifies an unsegmented address space.

13. The apparatus as recited in claim 10 further comprising a register coupled to the control circuit, wherein the register is configured to store a first indication, and wherein the control circuit is configured to generate the control input not to truncate in response to a first state of the indication even if truncating would otherwise be performed based on the operating mode and segment.

14. The apparatus as recited in claim 13, wherein the register is a model specific register.

15. The apparatus as recited in claim 10 wherein the circuit is configured to select between an output of a first adder having a first size equal to the size of the address and an output of a second adder having a second size equal to the predetermined number of bits.

16. The apparatus as recited in claim 10 wherein the circuit comprises a truncation circuit coupled to receive the address and to selectively substitute binary zeros for the most significant bits of the address above the predetermined number of bits in response to the control input.

17. A method comprising:

setting an indication in a register to a first state which prevents truncation of data reference addresses even if truncation would be performed according to an operating mode of a processor, wherein the processor includes the register;

performing a plurality of data references to determine a size of memory included in a system; and

setting the indication to a second state which allows truncation of data reference addresses according to the operating mode of the processor.

18. The method as recited in claim 17 wherein the performing comprises:

storing a first base address in a segment base address portion of a segment register;

performing a first plurality of the plurality of data references relative to the first segment base address;

storing a second base address in the segment base address portion of the segment register; and

performing a second plurality of the plurality of data references relative to the second segment base address.

19. The method as recited in claim 18 wherein each of the first base address and the second base address include at least one non-zero bit in a bit location subject to the truncation.

20. A computer readable medium comprising a plurality of instructions which, when executed, implement a method comprising:

setting an indication in a register to a first state which prevents truncation of data reference addresses even if truncation would be performed according to an operating mode of a processor, wherein the processor includes the register;

performing a plurality of data references to determine a size of memory included in a system; and

setting the indication to a second state which allows truncation of data reference addresses according to the operating mode of the processor.

21. The computer readable medium as recited in claim 20 wherein the performing comprises:

storing a first base address in a segment base address portion of a segment register;

performing a first plurality of the plurality of data references relative to the first segment base address;

storing a second base address in the segment base address portion of the segment register; and

performing a second plurality of the plurality of data references relative to the second segment base address.

22. The computer readable medium as recited in claim 21, wherein each of the first base address and the second base address include at least one non-zero bit in a bit location subject to the truncation.

23. A computer system comprising:

a memory; and

at least one processor coupled to the memory, wherein the processor is configured to perform one or more canonical checks for a data reference to the memory and a segment limit check on an effective address of the data reference, wherein a canonical check is a check to ensure, for an address of the data reference, that each address bit that is not included in an implemented address space is equal to a most significant address bit that is included in the implemented address space, and wherein the processor is configured to select, responsive to an operating mode and the segment corresponding to the data reference, one or more of;

a first result of the segment limit check and a second result of the one or more canonical checks for generating an exception for the data reference.

24. The computer system as recited in claim 23 wherein the one or more canonical checks include a first canonical check on the effective address and a second canonical check on a linear address of the data reference, and wherein the second result is the result of the first canonical check, and a third result is the result of the second canonical check, and wherein the processor is further configured to select the third result for generating the exception responsive to the operating mode and the segment.

25. The computer system as recited in claim 24, wherein the processor is configured to select the first result and not select the second result and the third result if the operating mode specifies a segmented address space in which a linear address size is less than or equal to 32 bits.

26. The computer system as recited in claim 24, wherein the processor is configured to select the first result if the operating mode specifies a segmented address space in which a linear address size in at least some segments is greater than 32 bits.

27. The computer system as recited in claim 26, wherein the processor is further configured to select the third result and not select the second result if the segment is a table segment.

28. The computer system as recited in claim 24 wherein the processor is configured to select the third result if the operating mode specifies an unsegmented address space.

29. The computer system as recited in claim 28 herein the processor is further configured to select the second result and not select the first result if the segment is a user segment.

30. The computer system as recited in claim 28 wherein the processor is further configured to select the first result and not select the second result if the segment is a table segment.

31. A computer system comprising:

a memory; and

at least one processor coupled to the memory, wherein the processor configured to generate an address of a data reference to the memory, wherein the processor is configured to truncate the address to a predetermined number of bits or not truncate the address dependent on a segment of the data reference and an operating mode, wherein the processor is configured to truncate the address if the operating mode specifies a segmented address space in which a linear address size in at least some segments is greater than 32 bits and the segment is a user segment.

32. The computer system as recited in claim 31 wherein the processor is configured to truncate the address if the operating mode specifies a segmented address space in which a linear address size is less than or equal to 32 bits.

33. The computer system as recited in claim 31 wherein the processor is configured not to truncate the address if the operating mode specifies an unsegmented address space.