Game system with graphics processor

• US 6,807,620 B1
• Filed: 02/11/2000
• Issued: 10/19/2004
• Est. Priority Date: 02/11/2000
• Status: Expired due to Term

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Okada, Toyoshi, Tanaka, Masayoshi, Oka, Masaaki, Ohba, Akio, Suzuoki, Masakazu, Hiroi, Toshiyuki, Yutaka, Teiji
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/502,671
• Time in Patent Office: 1,712 Days
• Field of Search: 345/541, 345/533, 345/535, 345/505, 712/2
• US Class Current: 712/2
• CPC Class Codes: A63F 2300/203 Image generating hardware
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

The present invention relates to the architecture and use of a computer system optimized for the efficient modeling of graphics. The computer system has a primary processor and a graphics processor. The primary processor has two vector processor units within it, one which is closely connected to central processor unit. Simultaneously performing complex modeling calculations on the first vector processor and CPU, and geometry transformation calculations on the second vector processor, allows for efficient modeling of graphics. Furthermore, the graphics processor is optimized to rapidly switch between data flow from the two vector processors. In addition, the graphics processor is able to render many pixels simultaneously, and has a local memory on the graphics processor chip that acts as a frame buffer, texture buffer, and z buffer. This allows a high fill rate to the frame buffer.

Claims

1. A primary processor for a computer system, said primary processor comprising:

a) a main bus;

b) a first processor unit connected to said main bus, said first processor unit having

i) a central processor unit;

ii) a first vector processor unit for performing first matrix calculations, said first vector processor unit connected to said central processor unit to enable said first vector processor unit to operate as a coprocessor for said central processor unit;

c) a second vector processor unit for performing second matrix calculations, said second vector processor unit connected to said main bus;

d) a graphics processor interface for arbitrating whether to transmit from said primary processor calculation results from said first processor unit or from said second vector processor unit, said graphics processor interface connected to said main bus and directly to said second vector processor unit.

2. The primary processor of claim 1, wherein said first matrix calculations comprise calculations for complex modeling of objects for graphical display.

3. The primary processor of claim 2, wherein said second matrix calculations comprise calculations for simple geometrical transformations of objects for graphical display.

4. The primary processor of claim 1, wherein said primary processor is implemented as an integrated circuit on a single substrate.

5. The primary processor of claim 1, wherein said first vector processor unit has at least four floating point processor pipelines.

6. The primary processor of claim 5, wherein said second vector processor unit has at least four floating point processor pipelines.

7. The primary processor of claim 1, wherein said main bus is at least 128-bits wide.

8. The primary processor of claim 7, wherein said central processor unit has an internal bus which is at least 128-bits wide.

9. The primary processor of claim 1, further comprising an image processing unit for decompressing high-resolution texture data from a compressed state.

10. The primary processor of claim 9, wherein said high-resolution texture data is encoded in the MPEG2 format.

11. The primary processor of claim 1, wherein said first vector processor unit includes a first vector interface for decompressing packed data.

12. The primary processor of claim 11, wherein said second vector processor unit includes a second vector interface for decompressing packed data.

13. The primary processor of claim 1, wherein said central processor unit includes a scratchpad memory, said scratchpad memory comprising SRAM and acting as a double buffer between said central processor unit and said main bus.

14. A computer system comprising:

a) a primary processor as in claim 1;

b) a graphics processor, implemented as an integrated circuit on a single substrate, for rendering three dimensional objects, said graphics processor, comprising

i) a graphics rendering engine;

ii) a local memory;

iii) a mode register for storing first data indicating when said graphics rendering engine is in a first mode corresponding to the receipt by said graphics rendering engine of data calculated by said first vector processor unit and said central processor unit, and for storing second data indicating when said graphics rendering engine is in a second mode corresponding to the receipt by said graphics rendering engine of data calculated by said second vector processor unit;

iv) a plurality of pairs of environmental registers, each of said pairs of environmental registers comprising a first register and a second register, each of said first registers storing data for determining how said graphics rendering engine processes data when said mode register stores said first data indicating said first mode, and each of said second registers storing data for determining how said graphics rendering engine processes data when said mode register stores said second data indicating said second mode; and

c) a graphics transfer bus connecting said graphics processor and said primary processor.

15. A primary processor for a computer system, said primary processor comprising:

a) a main bus;

b) a coprocessor bus;

c) an interface bus;

d) a central processor unit connected to said main bus and to said coprocessor bus;

e) a first vector processor unit for performing first matrix calculations, said first vector processor being connected to said main bus and directly to said central processing unit through said coprocessor bus to enable said first vector processor unit to operate as a coprocessor for said central processor unit;

f) a second vector processor unit for performing second matrix calculations, said second vector processor unit connected to said main bus and said interface bus;

g) a graphics processor interface for arbitrating whether to transmit from said primary processor calculation results from said first vector processor unit and said central processor unit, or from said second vector processor unit, said graphics processor interface connected to said main bus and directly to said second vector processor unit through said interface bus.

16. The primary processor of claim 15, wherein said first matrix calculations comprise calculations for complex modeling of objects for graphical display.

17. The primary processor of claim 16, wherein said second matrix calculations comprise calculations for simple geometrical transformations of objects for graphical display.

18. The primary processor of claim 15, wherein said primary processor is implemented as an integrated circuit on a single substrate.

19. The primary processor of claim 15, wherein said first vector processor unit has at least four floating point processor pipelines.

20. The primary processor of claim 19, wherein said second vector processor unit has at least four floating point processor pipelines.

21. The primary processor of claim 15, wherein said main bus is at least 128-bits wide.

22. The primary processor of claim 21, wherein said central processor unit has an internal bus which is at least 128-bits wide.

23. The primary processor of claim 15, further comprising an image processing unit for decompressing high-resolution texture data from a compressed state.

24. The primary processor of claim 23, wherein said high-resolution texture data is encoded in the MPEG2 format.

25. The primary processor of claim 15, wherein said first vector processor unit includes a first vector interface for decompressing packed data.

26. The primary processor of claim 25, wherein said second vector processor unit includes a second vector interface for decompressing packed data.

27. The primary processor of claim 15, wherein said central processor unit includes a scratchpad memory, said scratchpad memory comprising SRAM and acting as a double buffer between said central processing unit and said main bus.

28. A computer system comprising:

a) a primary processor as in claim 15;

b) a graphics processor for rendering three dimensional objects; and

c) a graphics transfer bus connecting said graphics processor and said primary processor.

29. The computer system of claim 28, wherein said graphics processor is implemented as an integrated circuit on a single substrate, and includes:

a) a graphics rendering engine, comprising;

i) a mode register for storing first data indicating when said graphics rendering engine is in a first mode corresponding to the receipt by said graphics rendering engine of data calculated by said first vector processor unit and said central processor unit, and for storing second data indicating when said graphics rendering engine is in a second mode corresponding to the receipt by said graphics rendering engine of data calculated by said second vector processor unit;

ii) a plurality of pairs of environmental registers, each of said pairs of environmental registers comprising a first register and a second register, each of said first registers storing data for determining how said graphics rendering engine processes data when said mode register indicates said first mode, and each of said second registers storing data for determining how said graphics rendering engine processes data when said mode register indicates said second mode; and

b) a local memory.

30. A graphics processor implemented as an integrated circuit on a single substrate, said graphics processor comprising:

a) a graphics rendering engine, said graphics rendering engine comprising;

i) a mode register for storing first data indicating when said graphics rendering engine is in a first mode corresponding to the receipt by said graphics rendering engine of data calculated by a first vector processor unit and a central processor unit, and for storing second data indicating when said graphics rendering engine is in a second mode corresponding to the receipt by said graphics rendering engine of data calculated by a second vector processor unit;

ii) a plurality of pairs of environmental registers, each of said pairs of environmental registers comprising a first register and a second register, each of said first registers storing data for determining how said graphics rendering engine processes data when said mode register stores said first data indicating said first mode, and each of said second registers storing data for determining how said graphics rendering engine processes data when said mode register stores said second data indicating said second mode; and

b) a local memory.

31. The graphics processor of claim 30, wherein said graphics rendering engine includes logic circuitry for implementing alpha blending.

32. The graphics processor of claim 30, wherein said graphics rendering engine includes logic circuitry for implementing fogging.

33. The graphics processor of claim 30, wherein said graphics rendering engine includes logic circuitry for a depth test to implement Z-buffering.

34. The graphics processor of claim 30, wherein said graphics rendering engine includes logic circuitry for implementing a destination alpha test.

35. The graphics processor of claim 30, wherein said graphics rendering engine includes logic circuitry for implementing an alpha test.

36. The graphics processor of claim 30, wherein said local memory includes a frame buffer, a texture buffer, and a z-buffer.

37. The graphics processor of claim 36, wherein said graphics rendering engine includes logic circuitry for filling said frame buffer with a rectangle of at least 16 pixels per clock cycle, and wherein said rectangle can be initiated at a different column for each row of a single polygon being rendered.

38. The graphics processor of claim 36, wherein said graphics rendering engine includes logic circuitry for implementing a moving stamp in writing to said frame buffer.

39. A method of performing graphics calculations comprising the steps of:

a) performing first calculations in a first data stream using a first processor, wherein said first calculations comprise calculations for complex modeling of objects for graphical display;

b) simultaneously performing second calculations in a second data stream using a second processor, wherein said second data stream is parallel to said first data stream and said second calculations comprise calculations for simple geometrical transformations of objects for graphical display.

40. The method of claim 39, further comprising the step of arbitrating whether said first calculations or said second calculations are transmitted to a graphics processor at any given time.

41. A method of programming a graphics program comprising the steps of:

a) designating first calculations to be processed by a first processor, wherein said first calculations comprise calculations for complex modeling of objects for graphical display;

b) designating second calculations to be calculated by a second processor, wherein said second calculations comprise calculations for simple geometrical transformations of objects for graphical display; and

c) processing said first calculations and said second calculations simultaneously; and

d) arbitrating whether said first calculations or said second calculations are transmitted to a graphics processor at any given time.

42. A system for performing graphics calculations comprising:

a) a first processor for performing first calculations and transmitting said first calculations in a first data stream, said first calculations comprising calculations for complex modeling of objects for graphical display;

b) a second processor for performing second calculations and transmitting said second calculations in a second data stream, said second data stream being parallel to said first data stream and said second calculations comprising calculations for simple geometrical transformation of objects for graphical display.

43. A system as in claim 42, further comprising an interface circuit for receiving said first data stream and said second data stream and for determining whether said first data stream or said second data stream is transmitted to a third processor for rendering.

44. A system for performing graphics calculations comprising:

a) a first processor for performing first graphics calculations and transmitting said first graphics calculations in a first data stream;

b) a second processor for performing second graphics calculations and transmitting said second graphics calculations in a second data stream;

c) an interface circuit for receiving said first data stream and said second data stream and for determining whether said first data stream or said second data stream is transmitted to a third processor for rendering;

wherein said first graphics calculations comprise calculations for complex modeling of objects for graphical display and said second graphics calculations comprise calculations for sample geometrical transformations of objects for graphical display.