Apparatus for and method of in-band clock compensation
First Claim
1. A method of in band clock compensation for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:
- inserting a first number of clock sync symbols into said input data stream on a periodic basis;
at said module, removing all but a second number of clock sync symbols from said input data stream;
determining the level of said queue in said module;
if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;
if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream; and
if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream.
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Abstract
A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.
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Citations
50 Claims
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1. A method of in band clock compensation for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:
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inserting a first number of clock sync symbols into said input data stream on a periodic basis;
at said module, removing all but a second number of clock sync symbols from said input data stream;
determining the level of said queue in said module;
if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;
if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream; and
if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23)
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13. An in band clock compensation system for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said system comprising:
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means for periodically inserting a first number of clock sync symbols into said data stream;
means for removing all but a second number of clock sync symbols from said input data stream; and
symbol stuffing means operative to;
insert a third number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;
insert a fourth number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;
insert a fifth number of clock sync symbols into said data stream if the level of said queue is above said upper threshold. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 24)
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25. A method in band clock compensation for use in a synchronous data processing system, said system including a plurality of processing modules each including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:
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periodically inserting a first number of clock sync symbols into the data stream before being received by a first module;
at each module, removing all but a second number of clock sync symbols from said input data stream;
determining the level of said queue in said module;
if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;
if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream; and
if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. An in band clock compensation system for use in a communications device, comprising:
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a receive line card adapted to periodically insert a first number of clock sync symbols into a data stream output therefrom; and
one or more switch cards, each switch card comprising a first first in first out (FIFO) queue and operative to;
remove all but a second number of clock sync symbols from said data stream; and
insert a third number of clock sync symbols into said data stream if the level of said first queue is below a lower threshold;
insert a fourth number of clock sync symbols into said data stream if the level of said first queue is above said lower threshold and below an upper threshold;
insert a fifth number of clock sync symbols into said data stream if the level of said first queue is above said upper threshold. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
remove all but a second number of clock sync symbols from said data stream; and
insert a third number of clock sync symbols into said data stream if the level of said first queue is below a lower threshold;
insert a fourth number of clock sync symbols into said data stream if the level of said first queue is above said lower threshold and below an upper threshold; and
insert a fifth number of clock sync symbols into said data stream if the level of said first queue is above said upper threshold.
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50. A clock compensation apparatus for use in a synchronous data processing module, comprising:
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an input buffer for receiving an input data stream wherein one or more clock sync symbols are periodically inserted therein;
means for removing all but a second number of clock sync symbols from said input data stream;
a first in first out (FIFO) queue adapted to receive said input data stream, said system means for inserting a first number of clock sync symbols into said data stream;
data processing operative to process said input data stream;
a clock compensation mechanism operative to;
insert a first number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;
insert a second number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;
insert a third number of clock sync symbols into said data stream if the level of said queue is above said upper threshold;
an output buffer for outputting the data stream output of said clock compensation mechanism.
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Specification