Apparatus for and method of in-band clock compensation

• US 6,807,638 B1
• Filed: 12/29/2000
• Issued: 10/19/2004
• Est. Priority Date: 12/29/2000
• Status: Expired due to Fees

• Current Assignee: Cisco Systems OIA 1988 Ltd (Cisco Systems, Inc.)
• Original Assignee: Cisco Systems OIA 1988 Ltd (Cisco Systems, Inc.)
• Inventors: Grinberg, Simon, Glaser, Ilan, Levi, Yehezkel, Moyal, Yehuda
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US09/751,428
• Time in Patent Office: 1,390 Days
• Field of Search: 713/400
• US Class Current: 713/400
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

Claims

1. A method of in band clock compensation for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:

inserting a first number of clock sync symbols into said input data stream on a periodic basis;

at said module, removing all but a second number of clock sync symbols from said input data stream;

determining the level of said queue in said module;

if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;

if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream; and

if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream.

2. The method according to claim 1, wherein said first number comprises three.

3. The method according to claim 1, wherein said second number comprises two.

4. The method according to claim 1, wherein said third number comprises two.

5. The method according to claim 1, wherein said fourth number comprises one.

6. The method according to claim 1, wherein said fifth number comprises zero.

7. The method according to claim 1, wherein said clock sync symbols comprise bytes having predetermined values.

8. The method according to claim 1, wherein said clock sync symbols comprise bytes having values 0x40, 0x41, 0x42 and 0x43.

9. The method according to claim 1, further comprising the step of modifying an error check sequence associated with said data stream in accordance with the clock sync symbols remaining in said data stream.

10. The method according to claim 1, wherein said upper threshold and said lower threshold is set to a value one half the size of said queue plus/minus a sixth number, respectively.

11. The method according to claim 10, wherein said sixth number comprises two.

12. The method according to claim 1, wherein the periodicity of insertion of said first number of clock sync symbols is determined so as to compensate for the worst case frequency variation between two modules.

23. The system according to claim 10, wherein said sixth number comprises two.

13. An in band clock compensation system for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said system comprising:

means for periodically inserting a first number of clock sync symbols into said data stream;

means for removing all but a second number of clock sync symbols from said input data stream; and

symbol stuffing means operative to;

insert a third number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;

insert a fourth number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;

insert a fifth number of clock sync symbols into said data stream if the level of said queue is above said upper threshold.

14. The system according to claim 13, wherein said first number comprises three.

15. The system according to claim 13, wherein said second number comprises two.

16. The system according to claim 13, wherein said third number comprises two.

17. The system according to claim 13, wherein said fourth number comprises one.

18. The system according to claim 13, wherein said fifth number comprises zero.

19. The system according to claim 13, wherein said clock sync symbols comprise bytes having predetermined values.

20. The system according to claim 13, wherein said clock sync symbols comprise bytes having values 0x40, 0x41, 0x42 and 0x43.

21. The system according to claim 13, further comprising means for modifying an error check sequence associated with said data stream in accordance with the clock sync symbols remaining in said data stream.

22. The system according to claim 13, wherein said upper threshold and said lower threshold is set to a value one half the size of said queue plus/minus a sixth number, respectively.

24. The system according to claim 13, wherein the periodicity of insertion of said first number of clock sync symbols is determined so as to compensate for the worst case frequency variation between two modules.

25. A method in band clock compensation for use in a synchronous data processing system, said system including a plurality of processing modules each including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:

periodically inserting a first number of clock sync symbols into the data stream before being received by a first module;

at each module, removing all but a second number of clock sync symbols from said input data stream;

determining the level of said queue in said module;

if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;

if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream; and

if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream.

26. The method according to claim 25, wherein said first number comprises three.

27. The method according to claim 25, wherein said second number comprises two.

28. The method according to claim 25, wherein said third number comprises two.

29. The method according to claim 25, wherein said fourth number comprises one.

30. The method according to claim 25, wherein said fifth number comprises zero.

31. The method according to claim 25, wherein said clock sync symbols comprise bytes having predetermined values.

32. The method according to claim 25, wherein said clock sync symbols comprise bytes having values 0x40, 0x41, 0x42 and 0x43.

33. The method according to claim 25, further comprising the step of modifying an error check sequence associated with said data stream in accordance with the clock sync symbols remaining in said data stream.

34. The method according to claim 25, wherein said upper threshold and said lower threshold is set to a value one half the size of said queue plus/minus a sixth number, respectively.

35. The method according to claim 34, wherein said sixth number comprises two.

36. The method according to claim 25, wherein the periodicity of insertion of said first number of clock sync symbols is determined so as to compensate for the worst case frequency variation between two modules.

37. An in band clock compensation system for use in a communications device, comprising:

a receive line card adapted to periodically insert a first number of clock sync symbols into a data stream output therefrom; and

one or more switch cards, each switch card comprising a first first in first out (FIFO) queue and operative to;

remove all but a second number of clock sync symbols from said data stream; and

insert a third number of clock sync symbols into said data stream if the level of said first queue is below a lower threshold;

insert a fourth number of clock sync symbols into said data stream if the level of said first queue is above said lower threshold and below an upper threshold;

insert a fifth number of clock sync symbols into said data stream if the level of said first queue is above said upper threshold.

38. The system according to claim 37, wherein said first number comprises three.

39. The system according to claim 37, wherein said second number comprises two.

40. The system according to claim 37, wherein said third number comprises two.

41. The system according to claim 37, wherein said fourth number comprises one.

42. The system according to claim 37, wherein said fifth number comprises zero.

43. The system according to claim 37, wherein said clock sync symbols comprise bytes having predetermined values.

44. The system according to claim 37, wherein said clock sync symbols comprise bytes having values 0x40, 0x41, 0x42 and 0x43.

45. The system according to claim 37, further comprising the step of modifying an error check sequence associated with said data stream in accordance with the clock sync symbols remaining in said data stream.

46. The system according to claim 37, wherein said upper threshold and said lower threshold is set to a value one half the size of said queue plus/minus a sixth number, respectively.

47. The system according to claim 46, wherein said sixth number comprises two.

48. The system according to claim 37, wherein the periodicity of insertion of said first number of clock sync symbols is determined so as to compensate for the worst case frequency variation between two modules.

49. The system according to claim 37, further comprising a transmit line card comprising a second first in first out (FIFO) queue, said transmit line card comprising means operative to:

remove all but a second number of clock sync symbols from said data stream; and

insert a third number of clock sync symbols into said data stream if the level of said first queue is below a lower threshold;

insert a fourth number of clock sync symbols into said data stream if the level of said first queue is above said lower threshold and below an upper threshold; and

insert a fifth number of clock sync symbols into said data stream if the level of said first queue is above said upper threshold.

50. A clock compensation apparatus for use in a synchronous data processing module, comprising:

an input buffer for receiving an input data stream wherein one or more clock sync symbols are periodically inserted therein;

means for removing all but a second number of clock sync symbols from said input data stream;

a first in first out (FIFO) queue adapted to receive said input data stream, said system means for inserting a first number of clock sync symbols into said data stream;

data processing operative to process said input data stream;

a clock compensation mechanism operative to;

insert a first number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;

insert a second number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;

insert a third number of clock sync symbols into said data stream if the level of said queue is above said upper threshold;

an output buffer for outputting the data stream output of said clock compensation mechanism.