Method to fill deep trench structures with void-free polysilicon or silicon

• US 6,809,005 B2
• Filed: 03/12/2003
• Issued: 10/26/2004
• Est. Priority Date: 03/12/2003
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Kulkarni, Subhash B., Chan, Kevin K., Ranade, Rajiv, Mathad, Gangadhara S.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US10/386,880
• Publication Number:
  US 20040180510A1
• Time in Patent Office: 594 Days
• Field of Search: 438/243-249, 438/386-392, 438/421-429, 438/430, 438/446, 257/300, 257/301
• US Class Current: 438/426
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a trench having sidewalls in a semiconductor substrate;

depositing a liner over the sidewalls; and

growing a filler within the trench from the liner.

2. The method of claim 1, wherein the liner is polysilicon.

3. The method of claim 2, wherein the filler is grown in a non-selective manner.

4. The method of claim 1, wherein the liner is silicon.

5. The method of claim 1, wherein the liner is between 5-15 nm thick.

6. The method of claim 1, wherein the liner is deposited using CVD.

7. The method of claim 6, wherein the CVD process is performed at a temperature between 560°

C. to 650°

C. and a pressure between 10 to 50 mTorr.

8. The method of claim 1, further comprising removing a native oxide from an exposed surface of the liner prior to the growing step.

9. The method of claim 8, wherein removing the native oxide is performed using buffered hydrofluoric acid.

10. The method of claim 9, further comprising performing an ozone treatment to remove byproducts formed with the buffered hydrofluoric acid.

11. The method of claim 1, wherein growing the filler is performed by RTCVD.

12. The method of claim 11, wherein the RTCVD is performed at a temperature of about 710°

C. and a pressure of about 15 mTorr.

13. The method of claim 1, further comprising, prior to growing the filler, the steps of:

forming a first mask over the liner;

depositing a second mask within the trench, the second mask covering a segment of the first mask;

removing portions of the first mask not covered by second mask;

removing the second mask;

removing portions of the liner not covered by the first mask; and

removing remaining portions of the first mask.

14. The method of claim 1, further comprising in situ doping the filler during the growing step.

15. The method of claim 1, wherein the trench is a high aspect ratio trench.

16. A method of fabricating a semiconductor device, comprising:

forming a trench having sidewalls in a semiconductor substrate;

depositing a first liner over the sidewalls;

depositing a second liner over the first liner;

forming a mask within the trench, the mask covering a segment of the second liner;

etching portions of the second liner not covered by mask;

removing the mask;

etching portions of the first liner not covered by the second liner;

etching remaining portions of the second liner; and

growing a filler within the trench from the first liner.

17. The method of claim 16, wherein the second liner is an oxide.

18. The method of claim 16, wherein the second liner is about 5 to 15 nm thick.

19. The method of claim 16, further comprising in situ doping the filler during the growing step.

20. The method of claim 16, wherein the step of forming the mask includes:

depositing the mask within the trench; and

recessing the mask to a desired depth within the trench.

21. The method of claim 16, wherein the step of etching the portions of the first liner is performed by isotropic etching.

22. The method of claim 16, wherein etching the remaining portions of the second liner is performed using buffered hydrofluoric acid.

23. A method of fabricating a semiconductor device, comprising:

providing a fill material within a trench, the trench having sidewalls in a semiconductor substrate;

exposing a void within the fill material; and

growing a healing material from the fill material to substantially fill the void.

24. The method of claim 23, wherein the healing material is selectively grown from the fill material.

25. The method of claim 23, wherein the healing material is epitaxial silicon.

26. The method of claim 23, wherein the healing material is grown at a temperature of about 650°

C. and a pressure of about 120 mTorr.

27. The method of claim 23, wherein the healing material is grown to provide a substantially planar surface for the fill material.

28. The method of claim 23, wherein the growing step includes substantially fill the trench with the healing material.

29. The method of claim 28, further comprising recessing the healing material to a desired depth within the trench.

30. A method of fabricating a capacitor, comprising:

forming a trench having sidewalls in a semiconductor substrate;

forming a buried plate in the semiconductor substrate adjacent to a lower portion of the trench;

applying a dielectric liner along the sidewalls in the lower portion of the trench;

forming a collar along the sidewalls in an upper portion of the trench;

forming a liner over the sidewalls; and

growing an inner electrode within the trench from the liner.

31. The method of claim 30, further comprising, prior to growing the inner electrode, the steps of:

forming a first mask over the liner;

depositing a second mask within the trench, the second mask covering a segment of the first mask;

removing portions of the first mask not covered by second mask;

removing the second mask;

removing portions of the liner not covered by the first mask; and

removing remaining portions of the first mask.

32. The method of claim 30, further comprising electrically connecting a transistor to the inner electrode.