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Integrated photosensor for CMOS imagers

  • US 6,809,008 B1
  • Filed: 08/28/2003
  • Issued: 10/26/2004
  • Est. Priority Date: 08/28/2003
  • Status: Expired due to Fees
First Claim
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1. A method for making an integrated CMOS-based imaging component, said method comprising the steps of:

  • providing at least one of a donor SOI wafer and a donor p-type wafer;

    providing a host CMOS wafer;

    optionally at least one of growing and at least partially converting said SOI wafer to p-type;

    growing at least one of an intrinsic or p-epitaxial layer on said donor wafer;

    growing a thermal oxide layer over said at least one of an intrinsic or p-epitaxial layer of said donor wafer;

    optionally forming alignment keys in a Si layer of said donor wafer;

    said alignment keys corresponding to base keys on said host wafer;

    defining an optically active, monocrystalline photosensor region in said donor wafer;

    fabricating at least one photodiode in said donor wafer using a plurality of ion implant steps;

    optionally forming an optically reflective structure over the top surface of said donor wafer;

    at least one of planarizing and preparing said donor wafer for bonding;

    at least one of planarizing and preparing said host wafer for bonding;

    aligning said host wafer with said donor wafer;

    bonding said host wafer with said donor wafer through an interface substantially proximate to metal interconnects of said host CMOS wafer;

    removing substrate material from said donor surface of the resulting donor/host composite structure;

    etching at least one via within at least one region of the donor/host composite structure'"'"'s top surface down to landing pads of said CMOS wafer;

    at least one of clearing, metallizing and plugging said vias with a metal;

    optionally re-planarizing the top surface of said donor/host composite structure;

    optionally forming at least one of a top side anti-reflective coating and a top side passivation layer; and

    opening access vias to I/O pads embedded in said CMOS wafer.

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