Wiring line and manufacture process thereof and semiconductor device and manufacturing process thereof

• US 6,809,021 B2
• Filed: 02/03/2003
• Issued: 10/26/2004
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohtani, Hisashi, Yamazaki, Shunpei
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US10/356,976
• Publication Number:
  US 20030132523A1
• Time in Patent Office: 631 Days
• Field of Search: 438/622, 438/627, 438/643, 438/653, 438/655, 438/657, 438/647, 438/687, 438/648, 438/656, 438/685
• US Class Current: 438/622
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;

patterning the multi-layered film to form a first wiring line;

forming an insulating film over the first wiring line;

forming a contact hole extending through the insulating film and reaching the first wiring line;

forming a second wiring line electrically connected with the first wiring line through the contact hole, and

wherein the second wiring line is connected with an upper surface of the second conductive layer at a bottom portion of the contact hole.

2. A method according to claim 1, wherein the second conductive layer comprising aluminum or titanium as its main component.

3. A method according to claim 1, wherein the wiring line is the gate line of a thin film transistor.

4. A method of manufacturing a semiconductor device comprising:

forming a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;

patterning the multi-layered film to form a first wiring line;

oxidizing the first wiring;

forming an insulating film over the first wiring line;

forming a contact hole extending through the insulating film and reaching the first wiring line;

forming a second wiring line electrically connected with the first wiring line through the contact hole, and

wherein the second wiring line is connected with an upper surface of the second conductive layer at a bottom portion of the contact hole.

5. A method according to claim 4, wherein the step of oxidizing the wiring line is conducted by anodizing.

6. A method according to claim 4, wherein the second conductive layer comprising aluminum or titanium as its main component.

7. A method according to claim 4, wherein the wiring line is the gate line of a thin film transistor.

8. A method of manufacturing a semiconductor device comprising:

forming a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer; and

a third conductive layer on the second conductive layer;

patterning the multi-layered film to form a first wiring line;

oxidizing the first wiring line;

forming an insulating film over the first wiring line;

forming a contact hole extending through the insulating film and reaching the first wiring line; and

forming a second wiring line electrically connected with the first wiring line through the contact hole,

wherein the second wiring line is connected with an upper surface of the second conductive layer at a bottom portion of the contact hole, and

wherein the second conductive layer has a width different from those of the first and the third conductive layers.

9. A method according to claim 8, wherein the second conductive layer comprising aluminum or titanium as its main component.

10. A method according to claim 8, wherein the first wiring line is the gate line of a thin film transistor.

11. A method of manufacturing a semiconductor device comprising:

forming a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;

patterning the multi-layered film to form a first wiring line;

reducing the width of the second conductive layer;

forming an insulating film over the first wiring line;

forming a contact hole extending through the insulating film and reaching the first wiring line;

forming a second wiring line electrically connected with the first wiring line through the contact hole, and

wherein the second wiring line is connected with an upper surface of the second conductive layer at a bottom portion of the contact hole.

12. A method according to claim 11, wherein the second conductive layer comprising aluminum or titanium as its main component.

13. A method according to claim 11, wherein the first wiring line is the gate line of a thin film transistor.