Low power differential-to-single-ended converter with good duty cycle performance

• US 6,809,566 B1
• Filed: 07/30/2003
• Issued: 10/26/2004
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Xin-LeBlanc, Jane
• Primary Examiner(s): Nguyen, Linh M.
• Application Number:
  US10/630,153
• Time in Patent Office: 454 Days
• Field of Search: 327/156, 327/147, 327/37, 327/40, 327/41, 327/47, 327/63, 327/65, 330/252, 331/17, 331/25, 375/373, 375/375, 375/376
• US Class Current: 327/156
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/033 Monostable circuits
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

Claims

1. A differential-to-single-ended (DSE) converter capable of receiving a positive differential input signal and a negative differential input signal and generating a single-ended output signal, said DSE converter comprising:

a first comparator having a non-inverting input coupled to said positive differential input signal and an inverting input coupled to said negative differential input signal;

a second comparator having an inverting input coupled to said positive differential input signal and a non-inverting input coupled to said negative differential input signal;

a first D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said first comparator;

a second D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said second comparator; and

a latch circuit having a first input coupled to an output of said first D flip-flop and a second input coupled to an output of said second D flip-flop, wherein a rising edge on an output of said first D flip-flop causes an output of said latch to change state and a rising edge on an output of said second D flip-flop causes said latch output to change state.

2. The differential-to-single-ended (DSE) converter as-set forth in claim 1, wherein said latch circuit comprises a first NOR gate having a first input coupled to said output of said first D flip-flop, a second input, and an output.

3. The differential-to-single-ended (DSE) converter as set forth in claim 2, wherein said latch circuit comprises a second NOR gate having a first input coupled to said output of said second D flip-flop, a second input coupled to said first NOR gate output, and an output coupled to said second input of said first NOR gate.

4. The differential-to-single-ended (DSE) converter as set forth in claim 3, wherein said first NOR gate is coupled to said first D flip-flop output by a first OR gate having a first input coupled to said first D flip-flop output, a second input coupled to Logic 0, and an output coupled to said first input of said first NOR gate.

5. The differential-to-single-ended (DSE) converter as set forth in claim 4, wherein said first NOR gate output is coupled to a reset input of said first D flip-flop.

6. The differential-to-single-ended (DSE) converter as set forth in claim 5, wherein said first NOR gate output is coupled to said reset input of said first D flip-flop via a buffer circuit.

7. The differential-to-single-ended (DSE) converter as set forth in claim 4, wherein said second NOR gate output is coupled to a reset input of said second D flip-flop.

8. The differential-to-single-ended (DSE) converter as set forth in claim 7, wherein said second NOR gate output is coupled to said reset input of said second D flip-flop via a buffer circuit.

9. The differential-to-single-ended (DSE) converter as set forth in claim 1, wherein a speed of said first comparator is determined by a biasing current of said first comparator and said biasing current is adjustable to match a frequency of said positive and negative differential input signals.

10. The differential-to-single-ended (DSE) converter as set forth in claim 1, wherein a speed of said second comparator is determined by a biasing current of said second comparator and said biasing current is adjustable to match a frequency of said positive and negative differential input signals.

11. A phase-locked loop (PLL) circuit comprising:

a voltage-controlled oscillator capable of receiving a control voltage and outputting a differential signal having a frequency controlled by said control voltage, said voltage-controlled oscillator comprising a ring oscillator containing a chain of delay cells having differential inputs and differential outputs;

a differential-to-single-ended (DSE) converter capable of receiving a positive differential input signal and a negative differential input signal from said voltage controlled oscillator and generating a single-ended output signal, said DSE converter comprising;

a first comparator having a non-inverting input coupled to said positive differential input signal and an inverting input coupled to said negative differential input signal;

a second comparator having an inverting input coupled to said positive differential input signal and a non-inverting input coupled to said negative differential input signal;

a first D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said first comparator;

a second D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said second comparator; and

a latch circuit having a first input coupled to an output of said first D flip-flop and a second input coupled to an output of said second D flip-flop, wherein a rising edge on an output of said first D flip-flop causes an output of said latch to change state and a rising edge on an output of said second D flip-flop causes said latch output to change state.

12. The phase-locked loop (PLL) circuit as set forth in claim 11, wherein said latch circuit comprises a first NOR gate having a first input coupled to said output of said first D flip-flop, a second input, and an output.

13. The phase-locked loop (PLL) circuit as set forth in claim 12, wherein said latch circuit comprises a second NOR gate having a first input coupled to said output of said second D flip-flop, a second input coupled to said first NOR gate output, and an output coupled to said second input of said first NOR gate.

14. The phase-locked loop (PLL) circuit as set forth in claim 13, wherein said first NOR gate is coupled to said first D flip-flop output by a first OR gate having a first input coupled to said first D flip-flop output, a second input coupled to Logic 0, and an output coupled to said first input of said first NOR gate.

15. The phase-locked loop (PLL) circuit as set forth in claim 14, wherein said first NOR gate output is coupled to a reset input of said first D flip-flop.

16. The phase-locked loop (PLL) circuit as set forth in claim 15, wherein said first NOR gate output is coupled to said reset input of said first D flip-flop via a buffer circuit.

17. The phase-locked loop (PLL) circuit as set forth in claim 14, wherein said second NOR gate output is coupled to a reset input of said second D flip-flop.

18. The phase-locked loop (PLL) circuit as set forth in claim 15, wherein said second NOR gate output is coupled to said reset input of said second D flip-flop via a buffer circuit.

19. The phase-locked loop (PLL) circuit as set forth in claim 11, wherein a speed of said first comparator is determined by a biasing current of said first comparator and said biasing current is adjustable to match a frequency of said positive and negative differential input signals.

20. The phase-locked loop (PLL) circuit as set forth in claim 11, wherein a speed of said second comparator is determined by a biasing current of said second comparator and said biasing current is adjustable to match a frequency of said positive and negative differential input signals.