Multi-channel circuit with current steering digital to analogue converters with minimized crosstalk

• US 6,809,673 B2
• Filed: 10/10/2002
• Issued: 10/26/2004
• Est. Priority Date: 10/10/2001
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Scanlan, Anthony, Purcell, John Patrick
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US10/268,273
• Publication Number:
  US 20030112164A1
• Time in Patent Office: 747 Days
• Field of Search: 341/144, 341/135, 341/136, 341/145, 341/118, 341/120, 327/108
• US Class Current: 341/144
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/662 Multiplexed conversion systems
• CPC Class Codes: H03M 1/745 with weighted currents

Abstract

A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Q_s1 to Q_sn) and current steering switches (Q_t1 and Q_f1 to Q_tn to Q_fn) for steering currents from the current source devices (Q_s1 to Q_sn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Q_c1 to Q_cn) are provided between the respective current source devices Q_s1 to Q_sn and the corresponding current steering switches (Q_t1 and Q_f1 to Q_tn and Q_fn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Q_t1 and Q_f1 to Q_tn and Q_fn) for minimizing crosstalk between the DACs (5). Gates of the cascode devices (Q_c1 to Q_cn) of DACs (5) are biased from corresponding cascode bias voltage circuits (25), and the gates of the cascode devices (Q_c1 to Q_cn) of each DAC (5) are isolated from the gates of the cascode devices (Q_c1 to Q_cn) of the other DACs (5) also for minimizing crosstalk.

Claims

1. A multi-channel integrated circuit comprising:

a plurality of channels,

a current steering digital to analogue converter (DAC) in each channel, each DAC comprising;

a plurality of current sources provided by corresponding current source devices coupled to a common supply rail,

the gates of the current source devices of the DACs being electrically tied together for mirroring a reference current, and being biased by a first bias voltage,

a plurality of current steering switches for steering currents from the current sources to either one of a pair of summing nodes of the corresponding DAC in response to a digital word for providing an analogue output signal on the summing nodes corresponding to the digital word,

a cascode device located between each current source device and the corresponding current steering switch for preventing capacitive feedthrough of voltage swings on the current steering switch to the gate of the corresponding current source device,

a reference circuit for generating the reference current for mirroring by the current source devices of the respective DACs, and for generating the first bias voltage,

a separate cascode bias voltage circuit being provided for each DAC for providing a second bias voltage for biasing the gates of the cascode devices of the corresponding DAC, the gates of the cascode devices of each DAC being electrically tied to the corresponding cascode bias voltage circuit for applying the second bias voltage to the cascode devices of the corresponding DAC, and being isolated from the gates of the cascode devices of the other DACs for preventing voltage swings on the current steering switches capacitively fed through to the gates of the corresponding cascode devices being transferred to the gates of the cascode devices of the other DACs for minimising crosstalk between the DACs.

2. A multi-channel circuit as claimed in claim 1 in which a reference current circuit is provided for each DAC for generating the reference current for the DAC, each reference current circuit being coupled to the common supply rail, and forming a part of the reference circuit.

3. A multi-channel circuit as claimed in claim 2 in which each reference current circuit comprises a first primary reference current device for generating the reference current for the corresponding DAC, a gate of each first primary reference current device being electrically tied to the gates of the current source devices of the corresponding DAC.

4. A multi-channel circuit as claimed in claim 3 in which the reference circuit comprises an amplifier having an output coupled to the gates of the respective first primary reference current devices for providing the first bias voltage thereto, the amplifier having a first input for receiving a reference voltage, and a second input connected to ground through a reference resistor, the respective first primary reference current devices being connected in parallel with each other between the common supply rail and ground through the reference resistor so that respective reference currents are forced through the respective first primary reference current devices as the amplifier maintains the voltage on the second input thereof equal to the reference voltage applied to the first input for establishing the respective reference currents through the first primary reference current devices.

5. A multi-channel circuit as claimed in claim 4 in which each cascode bias voltage circuit derives the second bias voltage for the gates of the cascode devices of the corresponding DAC from the output voltage of the amplifier of the reference circuit.

6. A multi-channel circuit as claimed in claim 5 in which each cascode bias voltage circuit is isolated from the output of the amplifier of the reference circuit by a corresponding secondary current mirror circuit.

7. A multi-channel circuit as claimed in claim 6 in which each secondary current mirror circuit comprises a first secondary reference current device, the gate of which is biased by the output of the amplifier, a second secondary reference current device being connected in series with the first secondary reference current device between the common supply rail and ground, and a third secondary reference current device the gate of which is electrically tied to the second secondary reference current device for mirroring the current through the second secondary reference current device in the third reference current device, the third reference current device being connected in series with a diode connected device between the common supply rail and ground for establishing the second bias voltage between the diode connected device and the third secondary reference current device.

8. A multi-channel circuit as claimed in claim 4 in which the reference current circuits are connected to the reference resistor at a common node, and the second input of the amplifier is connected to the common node.

9. A multi-channel circuit as claimed in claim 8 in which three external pins are provided to the multi-channel circuit, a first external pin being connected to the first input of the amplifier for applying the reference voltage thereto, a second external pin being provided as a ground pin, and a third external pin being connected to the common node for facilitating connection of the reference resistor between the common node and ground.

10. A multi-channel circuit as claimed in claim 4 in which each reference current circuit comprises a second primary reference current device corresponding to the cascode devices of the corresponding DACs, the second primary reference current device of each reference current circuit being coupled between the first primary reference current device and the reference resistor and in series therewith so that the corresponding reference current flows through the first and second primary reference current devices, a gate of each second primary current device being electrically tied to the gates of the cascade devices of the corresponding DAC.

11. A multi-channel circuit as claimed in claim 2 in which the reference current circuits are similar to each other.

12. A multi-channel circuit as claimed in claim 2 in which each reference current circuit is provided adjacent its corresponding DAC.

13. A multi-channel circuit as claimed in claim 1 in which the cascode bias voltage circuits are similar to each other.

14. A multi-channel circuit as claimed in claim 1 in which each cascode bias voltage circuit is located adjacent the corresponding DAC.

15. A multi-channel circuit as claimed in claim 1 in which the respective current sources of each DAC are binary weighted.

16. A multi-channel circuit as claimed in claim 1 in which the current source devices of each DAC are located relatively close to each other.

17. A multi-channel circuit as claimed in claim 1 in which the respective DACs are located relatively close to each other.

18. A method for minimising crosstalk between current steering DACs of a multi-channel circuit wherein each channel comprises one of the DACs, and each DAC comprises:

a plurality of current sources provided by corresponding current source devices, the gates of the current source devices being biased by a first bias voltage,

a plurality of current steering switches for steering currents from the current sources to either one of a pair of summing nodes of the corresponding DAC in response to a digital word for providing an analogue output signal on the summing nodes corresponding to the digital word, and wherein

a reference circuit is provided for generating the reference current for mirroring by the current source devices of the respective DACs, and for generating the first bias voltage,

the method comprising the steps of;

coupling a cascade device between each current source device and the corresponding current steering switch for preventing capacitive feedthrough of voltage swings on the current steering switches to the gate of the corresponding current source device,

providing a separate cascode bias voltage circuit for each DAC for providing a second bias voltage for biasing the gates of the cascode devices of the corresponding DAC, and

coupling the gates of the cascode devices of each DAC to the corresponding cascode bias voltage circuit for applying the second bias voltage to the cascode devices of the corresponding DAC so that the gates of the cascode devices of each DAC are isolated from the gates of the cascode devices of the other DACs.