Semiconductor integrated circuit, radio frequency identification transponder, and non-contact IC card

• US 6,809,952 B2
• Filed: 12/30/2002
• Issued: 10/26/2004
• Est. Priority Date: 03/29/2002
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Masui, Shoichi
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/330,063
• Publication Number:
  US 20030183699A1
• Time in Patent Office: 666 Days
• Field of Search: 365/145, 365/227, 365/192, 365/189.05
• US Class Current: 365/145
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07777 the antenna being of the inductive type
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

A rectifier circuit converts an alternating current into a direct-current voltage and outputs it as a power supply voltage. A ferroelectric holding circuit has a volatile holding circuit and a plurality of ferroelectric capacitors. Data held in the ferroelectric holding circuit has a read margin greater than that of data held in ferroelectric memory cells in a memory array. The ferroelectric holding circuit thus operates with reliability even if power that the semiconductor integrated circuit receives is low. Consequently, since the ferroelectric holding circuit is formed on the semiconductor integrated circuit to be implemented on an RFID transponder or a non-contact IC card, the communication range between the RFID transponder or non-contact IC card and a reader/writer can be extended.

Claims

1. A semiconductor circuit comprising:

a rectifier circuit for converting an alternating current into a direct-current voltage and outputting the direct-current voltage as a power supply voltage;

a memory array having a plurality of ferroelectric memory cells; and

a ferroelectric holding circuit having a volatile holding circuit and a plurality of ferroelectric capacitors.

2. The semiconductor integrated circuit according to claim 1, comprising

an internal voltage regulating circuit for generating for generating an internal supply voltage in accordance with said power supply voltage, said internal supply voltage being lower than said power supply voltage, wherein

said internal supply voltage is supplied to said ferroelectric holding circuit.

3. The semiconductor integrated circuit according to claim 1, comprising:

a data demodulator for demodulating a read command from an alternating current, the read command being a command for reading data from said ferroelectric holding circuit; and

a data modulator for modulating read data into an alternating current in accordance with said read command, the read data being read from said ferroelectric holding circuit.

4. The semiconductor integrated circuit according to claim 1, comprising

a control circuit for reading data held in said ferroelectric capacitors and transferring the data to said holding circuit at the start or supply of said power supply voltage.

5. The semiconductor integrated circuit according to claim 1, wherein said ferroelectric holding circuit includes:

a volatile latch circuit having two buffer circuits connected to each oilier at their inputs and outputs;

a pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node of said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

6. The semiconductor integrated circuit according to claim 1, wherein:

said ferroelectric holding circuit comprises a master latch circuit and a slave latch circuit connected in cascade; and

at least either one of said master latch circuit and said slave latch circuit includes;

a volatile latch circuit having two buffer circuits connected to each other at their inputs and outputs;

a pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node of said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

7. The semiconductor integrated circuit according to claim 1, wherein each of said ferroelectric memory coils of said memory array includes:

two ferroelectric capacitors each connected to a plate line at one end; and

two transfer gates for connecting the other ends of said ferroelectric capacitors to bit lines of a bit line pair, respectively.

8. The semiconductor integrated circuit according to claim 1, wherein each of said ferroelectric memory cells of said memory array includes:

a ferroelectric capacitor connected to a plate line at one end; and

a transfer gate for connecting the other end of said ferroelectric capacitor to a bit line.

9. A radio frequency identification transponder comprising an antenna coil for generating an alternating current in accordance with a magnetic field, and a semiconductor integrated circuit to be supplied with said alternating current, wherein said semiconductor integrated circuit includes:

a rectifier circuit for converting said alternating current into a direct-current voltage and outputting the direct-current voltage as a power supply voltage;

a memory array having a plurality of ferroelectric memory cells; and

a ferroelectric holding circuit having a volatile holding circuit and a plurality of ferroelectric capacitors.

10. The radio frequency identification transponder according to claim 9, comprising

an internal voltage regulating circuit for generating an internal supply voltage in accordance with said power supply voltage, said internal supply voltage being lower than said power supply voltage, wherein

said internal supply voltage is supplied to said ferroelectric holding circuit.

11. The radio frequency identification transponder according to claim 9, comprising:

a data demodulator for demodulating a read command from an alternating current, the read command being a command for reading data from said ferroelectric holding circuit; and

a data modulator for modulating read data into an alternating current in accordance with said read command, the read data being read from said ferroelectric holding circuit.

12. The radio frequency identification transponder according to claim 9, comprising

a control circuit for reading data held in said ferroelectric capacitors and transferring the data to said holding circuit at the start of supply of said power supply voltage.

13. The radio frequency identification transponder according to claim 9, wherein said ferroelectric holding circuit includes:

a volatile latch circuit having two buffer circuits connected to each other at their inputs and outputs;

a pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node of said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

14. The radio frequency identification transponder according to claim 9, wherein:

said ferroelectric holding circuit comprises a master latch circuit and a slave latch circuit connected in cascade; and

at least either one of said master latch circuit and said slave latch circuit includes;

a volatile latch circuit having two buffer circuits connected to each other at their inputs and outputs;

pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node of said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

15. The radio frequency identification transponder according to claim 9, wherein each of said ferroelectric memory cells of said memory array includes:

two ferroelectric capacitors each connected to a plate line at one end; and

two transfer gates for connecting the other ends of said ferroelectric capacitors to bit lines of a bit line pair, respectively.

16. The radio frequency identification transponder according to claim 9, wherein each of said ferroelectric memory cells of said memory array includes:

a ferroelectric capacitor connected to a plate line at one end; and

a transfer gate for connecting the other end of said ferroelectric capacitor to a bit line.

17. A non-contact IC card comprising an antenna coil for generating an alternating current in accordance with a magnetic field, and a semiconductor integrated circuit to be supplied with said alternation current, wherein said semiconductor integrated circuit includes:

a rectifier circuit for converting said alternating current into a direct-current voltage and outputting the direct-current voltage as a power supply voltage;

a memory array having a plurality of ferroelectric memory cells; and

a ferroelectric holding circuit having a volatile holding circuit and a plurality of ferroelectric capacitors.

18. The non-contact IC card according to claim 17, comprising

an internal voltage regulating circuit for generating an internal supply voltage in accordance with said power supply voltage, said internal supply voltage being lower than said power supply voltage, wherein

said internal supply voltage is supplied to said ferroelectric holding circuit.

19. The non-contact IC card according to claim 17, comprising:

a data demodulator for demodulating a read command from an alternating current, the read command being a command for reading data from said ferroelectric holding circuit; and

a data modulator for modulating read data into an alternating current in accordance with said read command, the read data being read from said ferroelectric holding circuit.

20. The non-contact IC card according to claim 17, comprising

a control circuit, for reading data held in said ferroelectric capacitors and transferring the data to said holding circuit at the start of supply of said power supply voltage.

21. The lion-contact IC card according to claim 17, wherein said ferroelectric holding circuit includes:

a volatile latch circuit having two buffer circuits connected to each other at their inputs and outputs;

a pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node or said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

22. The non-contact IC card according to claim 17, wherein:

said ferroelectric holding circuit comprises a master latch circuit and a slave latch circuit connected in cascade; and

at least either one of said master latch circuit and said slave latch circuit includes;

a volatile latch circuit having two buffer circuits connected to each other at their inputs and outputs;

pair of first ferroelectric capacitors connected in series between a first plate line and a second plate line, wherein an intermediate node of said first ferroelectric capacitors is connected to the input of one of said buffer circuits;

a pair of second ferroelectric capacitors connected in series between said first plate line and said second plate line, wherein an intermediate node of said second ferroelectric capacitors is connected to the input of the other of said buffer circuits; and

a switch circuit for connecting power supply terminals of said buffer circuits to a power supply line.

23. The non-contact IC card according to claim 17, wherein each of said ferroelectric memory cells of said memory array includes:

two ferroelectric capacitors each connected to a plate line at one end; and

two transfer gates for connecting the other ends of said ferroelectric capacitors to bit lines of a bit line pair, respectively.

24. The non-contact IC card according to claim 17, wherein each of said ferroelectric memory cells of said memory array includes:

a ferroelectric capacitor connected to a plate line at one end; and

a transfer gate for connecting the other end of said ferroelectric capacitor to a bit line.