Memory cells enhanced for resistance to single event upset

• US 6,809,957 B2
• Filed: 02/26/2004
• Issued: 10/26/2004
• Est. Priority Date: 04/17/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lesea, Austin H.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/787,331
• Publication Number:
  US 20040165418A1
• Time in Patent Office: 243 Days
• Field of Search: 365/154, 365/72, 365/148, 365/181, 365/188
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information

Abstract

Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Claims

1. A memory cell formed of complementary NMOS and PMOS transistors, comprising:

a first inverter having a first output node, a first NMOS transistor and a first PMOS transistor, the first output node located between the first NMOS transistor and the first PMOS transistor, the first NMOS transistor and the first PMOS transistor having respective first gates, the first gates providing respective first input nodes of the first inverter;

a second inverter having a second output node, a second NMOS transistor and a second PMOS transistor, the second output node located between the second NMOS transistor and the second PMOS transistor, the second NMOS transistor and the second PMOS transistor having respective second gates, the second gates providing respective second input nodes of the second inverter;

a third NMOS transistor and a third PMOS transistor;

a fourth NMOS transistor and a fourth PMOS transistor;

the third NMOS transistor and the fourth NMOS transistor commonly coupled to receive a first gate bias voltage;

the third PMOS transistor and the fourth PMOS transistor commonly coupled to receive a second gate bias voltage;

the third NMOS transistor having source and drain coupled between a gate of the first NMOS transistor and the second output node;

the fourth NMOS transistor having source and drain coupled between a gate of the second NMOS transistor and the first output node;

the third PMOS transistor having source and drain coupled between a gate of the first PMOS transistor and the second output node; and

the fourth PMOS transistor having source and drain coupled between a gate of the second PMOS transistor and the first output node.

2. The memory cell of claim 1, wherein the first gate bias voltage and the second gate bias voltage are complements of one another.

3. The memory cell of claim 1, wherein the memory cell comprises a configuration memory cell of a programmable logic device.

4. The memory cell of claim 1, wherein the first gate bias voltage comprises a sub-threshold voltage for the third and fourth MOS transistors, and the second gate bias voltage comprises a sub-threshold voltage for the third and fourth PMOS transistors.