SRAM array with temperature-compensated threshold voltage

• US 6,809,968 B2
• Filed: 02/18/2003
• Issued: 10/26/2004
• Est. Priority Date: 08/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Marr, Kenneth W.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/368,068
• Publication Number:
  US 20030151956A1
• Time in Patent Office: 616 Days
• Field of Search: 365/185.01, 365/185.24, 365/185.25, 365/185.27, 365/185.18
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Systems and methods are provided for a temperature-compensated threshold voltage V_T. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated V_TN. According to one embodiment, a temperature-based modulation of a V_BB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated V_TN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a V_T-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

Claims

1. A method of providing a temperature-compensated pull-down threshold voltage V_T, comprising:

comparing a controlled temperature-based voltage reference to a V_T-based voltage; and

generating a temperature-compensated bias voltage for a transistor body terminal based on the comparison between the temperature-based voltage reference and the V_T-based voltage.

2. The method of claim 1, wherein comparing a controlled temperature-based voltage reference to a V_T-based voltage includes comparing a temperature-independent voltage reference to a V_T-based voltage.

3. The method of claim 1, wherein comparing a controlled temperature-based voltage reference to a V_T-based voltage includes comparing a controlled temperature-dependent voltage reference to a V_T-based voltage.

4. The method of claim 3, wherein comparing a controlled temperature-dependent voltage reference to a V_T-based voltage includes comparing a voltage reference with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage) to a V_T-based voltage.

5. The method of claim 1, wherein generating a temperature-compensated bias voltage for a transistor body terminal includes charging the transistor body terminal to increase the V_T-based voltage when the temperature-based voltage reference is larger than the V_T-based voltage.

6. The method of claim 5, wherein comparing a controlled temperature-based voltage reference to a V_T-based voltage includes adjusting the V_T-based voltage based on whether the transistor body terminal is being charged to provide a hysteresis effect in compensating the pull-down threshold voltage V_T.

7. A method of providing a temperature-compensated pull-down threshold voltage V_T, comprising:

comparing a controlled temperature-based voltage reference to a V_T-dependent voltage, including determining whether the V_T-dependent voltage is less than a first reference voltage that corresponds to a V_Tmin or more than a second reference voltage that corresponds to a V_Tmax; and

generating a temperature-compensated bias voltage for a transistor body terminal based on the comparison between the temperature-based voltage reference and the V_T-dependent voltage, including charging the transistor body terminal of a triple-well transistor until the V_T-dependent voltage is more than the second reference voltage that corresponds to the V_Tmax in response to determining that the V_T-dependent voltage is less than the first reference voltage that corresponds to the V_Tmin.

8. The method of claim 7, wherein at least one of the first reference voltage and the second reference voltage include a temperature-independent reference voltage.

9. The method of claim 7, wherein at least one of the first reference voltage and the second reference voltage include a voltage reference with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage).

10. A method of providing a temperature-compensated pull-down threshold voltage V_T, comprising:

comparing a controlled temperature-based voltage reference to a V_T-dependent voltage, including;

providing a comparator having a first input, a second input and an output;

receiving the V_T-dependent voltage at the first input of the comparator;

receiving the controlled temperature-based voltage reference at the second input of the comparator; and

providing a control signal indicative based on the comparison between the controlled temperature-based voltage reference to the V_T-dependent voltage; and

generating a temperature-compensated bias voltage for a transistor body terminal based on the comparison between the temperature-based voltage reference and the V_T-dependent voltage, including;

providing a charge pump to receive the control signal and coupling the charge pump to a number of transistor body terminals; and

in response to receiving the control signal at the charge pump, using the charge pump to charge the number of transistor body terminals.

11. The method of claim 10, wherein the controlled temperature-based reference includes a temperature-independent reference voltage.

12. The method of claim 10, wherein the controlled temperature-based reference includes a voltage reference with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage).

13. The method of claim 10, wherein comparing a controlled temperature-based voltage reference to a V_T-based voltage includes adjusting the V_T-based voltage based on whether the transistor body terminal is being charged to provide a hysteresis effect in compensating the pull-down threshold voltage V_T.

14. The method of claim 10, wherein:

providing a control signal indicative based on the comparison between the controlled temperature-based voltage reference to a V_T-dependent voltage includes providing a control signal indicative of whether the V_T-dependent voltage is less than a first reference voltage or more than a second reference voltage; and

in response to receiving the control signal at the charge pump, using the charge pump to charge the number of transistor body terminals includes;

in response to receiving a control signal indicating that the V_T-dependent voltage is less than the first reference voltage, charging the body terminal; and

in response to receiving a control signal indicating that the V_T-dependent voltage is more than the second reference voltage, ceasing to charge the body terminal.

15. A method of providing a temperature-compensated pull-down threshold voltage V_T, comprising:

determining whether a V_T-dependent voltage is less than a first reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage) or more than a second reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage); and

in response to determining that the V_T-dependent voltage is less than the first reference voltage that corresponds to the V_Tmin, charging a transistor body terminal until the V_T-dependent voltage is more than the second reference voltage that corresponds to the V_Tmax.

16. A method of providing a temperature-compensated pull-down threshold voltage V_T for at least one transistor, comprising:

providing at least one triple-well transistor, wherein each triple-well transistor includes;

a p-substrate;

a p-well isolated from the p-substrate by an n-tub electrically coupled to an n-well;

an NMOS transistor formed within the isolated p-well;

an n+ contact for the n-well; and

a V_BB p+ contact for the p-well, wherein the V_BB p+ contact functions as a body terminal;

determining whether a V_T-dependent voltage is less than a first reference voltage that corresponds to a V_Tmin or more than a second reference voltage that corresponds to a V_Tmax; and

in response to determining that the V_T-dependent voltage is less than the first reference voltage that corresponds to the V_Tmin, charging the transistor body terminal of each of the plurality of triple-well transistors until the V_T-dependent voltage is more than the second reference voltage that corresponds to the V_Tmax.

17. A method of providing a temperature-compensated pull-down threshold voltage V_T for a memory array, comprising:

providing an LL4TCMOS SRAM array that includes a plurality of transistors with a body terminal and a threshold voltage V_T;

determining whether a V_T-dependent voltage is less than a first reference voltage that corresponds to a V_Tmin or more than a second reference voltage that corresponds to a V_Tmax; and

in response to determining that the V_T-dependent voltage is less than the first reference voltage that corresponds to the V_Tmin, charging the transistor body terminal of each of the plurality of transistors until the V_T-dependent voltage is more than the second reference voltage that corresponds to the V_Tmax.

18. A method of providing a temperature-compensated pull-down threshold voltage V_T for a memory array, comprising:

providing an LL4TCMOS SRAM array that includes a plurality of triple-well transistors, wherein each triple-well transistor includes;

a p-substrate;

a p-well isolated from the p-substrate by an n-tub electrically coupled to an n-well;

an NMOS transistor formed within the isolated p-well;

an n+ contact for the n-well; and

a V_BB P+ contact for the p-well, wherein the V_BB p+ contact functions as a body terminal;

determining whether a V_T-dependent voltage is less than a first reference voltage that corresponds to a V_Tmin or more than a second reference voltage that corresponds to a V_Tmax; and

in response to determining that the V_T-dependent voltage is less than the first reference voltage that corresponds to the V_Tmin, charging the transistor body terminal of each of the plurality of triple-well transistors until the V_T-dependent voltage is more than the second reference voltage that corresponds to the V_Tmax.

19. A method of providing a temperature-compensated pull-down threshold voltage V_T for a memory array, comprising:

providing a comparator having a first input, a second input, and an output;

providing a charge pump;

coupling the charge pump to the comparator and to a body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array;

receiving a V_T-dependent voltage at the first input of the comparator;

receiving a reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage) at the second input of the comparator;

providing a control signal to the charge pump, wherein the control signal is indicative of whether the V_T-dependent voltage is less than a first reference voltage or more than a second reference voltage;

in response to receiving a control signal indicating that the V_T-dependent voltage is less than the first reference voltage, charging the body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array; and

in response to receiving a control signal indicating that the V_T-dependent voltage is more than the second reference voltage, ceasing to charge the body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array.

20. A method of forming a transistor body bias generator, comprising:

providing a charge pump with an output adapted to couple to a body terminal of at least one transistor;

providing a comparator with a first input, a second input and an output;

coupling the first input to a reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage);

coupling the second input to a V_T-dependent voltage; and

coupling the output to the charge pump to present a control signal to the charge pump, wherein the charge pump is adapted to compensate for temperature changes by selectively charging the body terminal of the at least one transistor in response to the control signal.

21. A method of forming a memory array, comprising:

providing a plurality of triple-well transistors having a body terminal and a threshold voltage V_T;

providing a comparator having a first input, a second input, and an output;

providing a charge pump;

coupling the charge pump to the body terminal of each of the plurality of triple-well transistors;

coupling a V_T-dependent voltage at the first input of the comparator;

coupling a reference voltage at the second input of the comparator; and

coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the V_T-dependent voltage and the reference voltage.

22. A method of forming a memory array, comprising:

providing a bank of transistors having a body terminal and a threshold voltage V_T;

providing a memory array, including providing a plurality of transistors having a body terminal;

providing a comparator having a first input, a second input, and an output;

providing a charge pump;

coupling the charge pump to the body terminal for the bank of transistors and to the body terminal of each of the plurality of transistors in the memory array;

coupling a V_T-dependent voltage from the bank of transistors to the first input of the comparator;

coupling a reference voltage at the second input of the comparator; and

coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the V_T-dependent voltage and the reference voltage.

23. A method-of forming a memory array, comprising:

providing a bank of transistors having a body terminal and a threshold voltage V_T;

providing a LL4TCMOS SRAM array, including providing a plurality of transistors having a body terminal;

providing a comparator having a first input, a second input, and an output;

providing a charge pump;

coupling the charge pump to the body terminal for the bank of transistors and to the body terminal of each of the plurality of transistors in the LL4TCMOS SRAM array;

coupling a V_T-dependent voltage from the bank of transistors to the first input of the comparator;

coupling a reference voltage at the second input of the comparator; and

coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the V_T-dependent voltage and the reference voltage.

24. A method of forming a memory array, comprising:

providing a bank of triple-well transistors having a body terminal and a threshold voltage V_T;

providing a LL4TCMOS SRAM array, including providing a plurality of triple-well transistors having a body terminal;

providing a comparator having a first input, a second input, and an output;

providing a charge pump;

coupling the charge pump to the body terminal for the bank of triple-well transistors and to the body terminal of each of the plurality of triple-well transistors in the LL4TCMOS SRAM array;

coupling a V_T-dependent voltage from the bank of triple-well transistors to the first input of the comparator;

coupling a reference voltage at the second input of the comparator; and

coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the V_T-dependent voltage and the reference voltage.