Flash memory device capable of repairing a word line

• US 6,809,973 B2
• Filed: 08/04/2003
• Issued: 10/26/2004
• Est. Priority Date: 12/27/2002
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Ju Yeab
• Primary Examiner(s): Lam, David
• Application Number:
  US10/633,730
• Publication Number:
  US 20040125669A1
• Time in Patent Office: 449 Days
• Field of Search: 365/200, 365/49, 365/230.06, 365/185.33
• US Class Current: 365/200
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

Disclosed is the flash memory device capable of repairing the word line. Fail word lines are repaired using redundancy cells for repairing bit lines by combining X/Y addresses, whereby repair in the direction of the bit line as well as repair in the direction of the word line is made possible. Therefore, it is possible to prevent degradation in the yield and improve reliability of the device.

Claims

1. A word line repair circuit in a flash memory device, comprising:

a main cell array in which a plurality of cell are classified in a I/O block unit;

a redundancy cell array consisting of repair blocks in which the number of word lines is equivalent to the number of columns constituting the I/O block and the number of cells connected to the word line is equivalent to the number of the I/O block;

a CAM cell array for storing information including information on a fail word line of the main cell array and connection information on the repair block instead of the fail word line;

a word line voltage switching unit for transferring a word line voltage applied to the fail word line to the redundancy cell array according to information on the fail word line; and

a word line select means enabled by the connection information, for selecting a word line of the repair block corresponding to a column of the I/O block according to the column select signal of the main cell array and then applying the word line voltage to the selected word line,

wherein data to be stored through the fail word line are sequentially stored through a corresponding column of the repair block in a I/O block unit, thereby repairing the fail word line.

2. The word line repair circuit as claimed in claim 1, wherein the I/O block is 16 in number.

3. The word line repair circuit as claimed in claim 1, wherein the I/O block consists of 1024 word lines and 64 columns and the repair block consists of 64 word lines and 16 columns.

4. The word line repair circuit as claimed in claim 1, wherein the word line voltage switching unit comprises:

first switching means each connected between the word line voltage supply terminal and the word line of the main cell array and driven by a fail word line signal of the CAM cell array;

an inverter for inverting the fail word line signal; and

a second switching means for transferring the word line voltage to the word line select means according to the fail word line inverted signal from the inverter.

5. The word line repair circuit as claimed in claim 4, wherein the first switching means and the second switching means are field effect transistors.

6. The word line repair circuit as claimed in claim 1, wherein the word line select means is provided every repair block.

7. The word line repair circuit as claimed in claim 1, wherein the word line select means comprises:

a first switching means driven by an enable signal depending on the connection information stored at the CAM cell array, for switching the word line voltage; and

a plurality of switching means each connected between the first switching means and the word line of the repair block, for switching the word line voltage to a word line of a repair block corresponding to a corresponding column according to the column select signal of the main cell array.