DRAM technology compatible processor/memory chips

• US 6,809,985 B2
• Filed: 07/09/2002
• Issued: 10/26/2004
• Est. Priority Date: 02/26/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/191,332
• Publication Number:
  US 20020176314A1
• Time in Patent Office: 840 Days
• Field of Search: 365/230.06, 365/185.17, 365/149, 326/105, 326/106
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Claims

1. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

2. The programmable logic array of claim 1, wherein the first logic plane and the second logic plane each comprise NOR planes.

3. The programmable logic array of claim 1, wherein the substrate is a bulk semiconductor.

4. The programmable logic array of claim 1, wherein the electrical contact includes a polysilicon plug.

5. The programmable logic array of claim 1, wherein the working surface of the substrate includes an ins insulating layer formed on top of an underlying semiconductor.

6. The programmable logic array of claim 1, wherein the programmable logic array is operatively coupled to a computer system.

7. The programmable logic array of claim 1, wherein the stacked capacitor includes a fin type capacitor.

8. The logic array of claim 1, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the MOSFET.

9. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

10. The programmable logic array of claim 9, wherein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

11. The programmable logic array of claim 9, wherein the first logic plane includes inverters adapted to generate complements of the input signals.

12. The programmable logic array of claim 9, wherein the electrical contact includes a polysilicon plug.

13. The programmable logic array of claim 9, the stacked capacitor includes a fin type capacitor.

14. The programmable logic array of claim 9, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

15. The programmable logic array of claim 9, wherein the transistor is a metal oxide semiconductor field effect transistor.

16. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;

arid

an electrical contact that couples the stacked capacitor to a gate of the transistor.

17. The programmable logic array of claim 16, herein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

18. The programmable logic array of claim 16, wherein the first logic plane includes inverters that are adapted to generate complements of the input signals.

19. The programmable logic array of claim 16, the electrical contact includes a polysilicon plug.

20. The programmable logic array of claim 16, the cup-shaped stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

21. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to the gate of the transistor.

22. The programmable Logic array of claim 21, wherein the gate oxide has a thickness of less than 100 angstroms.

23. The programmable logic array of claim 21, wherein the gate oxide acts as a tunneling oxide.

24. The programmable logic array of claim 21, wherein the implemented logical function includes at least one NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

25. The programmable logic array of claim 21, wherein the first logic plane includes inverters that are adapted to generate complements of the input signals.

26. The programmable logic array of claim 21, wherein the electrical contact includes a polysilicon plug.

27. The programmable logic array of claim 21, wherein the stacked capacitor includes a fin type capacitor.

28. The programmable logic array of claim 21, the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

29. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and

an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

30. The programmable logic array of claim 29, wherein the bottom plate serves as a storage node.

31. The programmable logic array of claim 29, wherein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.

32. The programmable logic array of claim 29, the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

33. The programmable logic array of claim 29, wherein the first logic plane includes inverters that generate complements of the input signals.

34. The programmable logic array of claim 29, wherein the electrical contact includes a polysilicon plug.

35. The programmable logic array of claim 29, wherein the stacked capacitor includes a fin type capacitor.

36. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and

an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

37. The programmable logic array of claim 36, herein the bottom plate serves as a storage node.

38. The programmable logic array of claim 36, herein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.

39. The programmable logic array of claim 36, wherein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

40. The programmable logic array of claim 36, wherein the first logic plane includes inverters that are adapted to generate complements of the input signals.

41. The programmable logic array of claim 36, the electrical contact includes a polysilicon plug.

42. A programmable logic al-ray, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

43. The programmable logic array of claim 42, herein the gate oxide acts as a tunneling oxide.

44. The programmable logic array of claim 42, wherein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

45. The programmable logic array of claim 42, wherein the first logic plane includes inverters that are adapted to generate complements of the input signals.

46. The programmable logic array of claim 43, wherein the electrical contact includes a polysilicon plug.

47. The programmable logic array of claim 42, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

48. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide, the gate oxide being adapted to act as a tunneling oxide;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.