Method and apparatus for modeling using a hardware-software co-verification environment
First Claim
1. A system for modeling a hardware design for carrying out an operation wherein the hardware design includes:
- an integrated circuit having including a processor and an internal bus;
a hardware model containing the integrated circuit;
a bus functional model employing a first system interface unit and a second system interface unit;
means for disabling the processor of the integrated circuit, wherein disabling the processor is accomplished by using initialization code to put the processor into an endless loop;
means for simulating the operation of the processor; and
means for modeling the internal bus of the integrated circuit and providing signals which would ordinarily appear on the internal bus of the hardware design.
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Accused Products
Abstract
A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.
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Citations
27 Claims
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1. A system for modeling a hardware design for carrying out an operation wherein the hardware design includes:
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an integrated circuit having including a processor and an internal bus;
a hardware model containing the integrated circuit;
a bus functional model employing a first system interface unit and a second system interface unit;
means for disabling the processor of the integrated circuit, wherein disabling the processor is accomplished by using initialization code to put the processor into an endless loop;
means for simulating the operation of the processor; and
means for modeling the internal bus of the integrated circuit and providing signals which would ordinarily appear on the internal bus of the hardware design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A hardware model including an integrated circuit having a processor and an internal bus, the hardware model including:
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means for disabling the processor by using initialization code to put the processor into an endless loop; and
means for allowing a direct communication between the a bus functional model and the hardware model to send interrupt service routines without passing through the processor. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A system for modeling a hardware design for carrying out an operation wherein the hardware design includes an integrated circuit having a processor and an internal bus, the system comprising:
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a simulator circuit simulating the hardware design and including the integrated circuit;
an instruction set simulator for representing an operation of the processor; and
means for disabling the processor by putting the processor into an endless loop. - View Dependent Claims (17, 18, 19)
a hardware model containing the integrated circuit having the processor and the internal bus;
a bus functional model for interfacing the instruction set simulator to the simulator circuit, wherein the simulator circuit can carry out the operation operate without intervention of the processor for determining whether the hardware design is correct; and
a transfer memory to pass system interrupts between the hardware model and the bus functional model.
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18. The system for modeling a hardware of claim 17 wherein the hardware model simulates the integrated circuit by communicating with the bus functional model through a system interface unit.
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19. The system of claim 16 wherein the instruction set simulator is external to the simulator circuit and executes interrupt service routines.
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20. A hardware model including an integrated circuit, the integrated circuit comprising a processor and an internal bus, the hardware model including:
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means for effectively putting the processor into an endless loop; and
means for allowing a direct communication between the a bus functional model and the hardware model to send interrupt service routines without passing through the processor. - View Dependent Claims (21)
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22. A method of modeling an integrated circuit, comprising the following steps:
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putting a central processing unit (CPU) into an inactive state by effectively placing the CPU into an endless loop;
servicing an instruction set simulator (ISS) access into peripheral devices;
servicing peripheral-generated cycles; and
servicing peripheral-generated interrupt requests. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification