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Method and apparatus for modeling using a hardware-software co-verification environment

  • US 6,810,373 B1
  • Filed: 08/11/2000
  • Issued: 10/26/2004
  • Est. Priority Date: 08/13/1999
  • Status: Expired due to Term
First Claim
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1. A system for modeling a hardware design for carrying out an operation wherein the hardware design includes:

  • an integrated circuit having including a processor and an internal bus;

    a hardware model containing the integrated circuit;

    a bus functional model employing a first system interface unit and a second system interface unit;

    means for disabling the processor of the integrated circuit, wherein disabling the processor is accomplished by using initialization code to put the processor into an endless loop;

    means for simulating the operation of the processor; and

    means for modeling the internal bus of the integrated circuit and providing signals which would ordinarily appear on the internal bus of the hardware design.

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