Multimedia interface having a processor and reconfigurable logic

• US 6,810,434 B2
• Filed: 08/14/2001
• Issued: 10/26/2004
• Est. Priority Date: 12/29/1997
• Status: Expired due to Fees

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Inventors: Rostoker, Michael D., Muthujumaraswathy, Kumaraguru
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/929,515
• Publication Number:
  US 20020026539A1
• Time in Patent Office: 1,169 Days
• Field of Search: 710/5, 710/40, 710/305, 713/100, 713/300, 713/322, 713/324, 712/210, 712/11, 712/15, 712/16
• US Class Current: 710/5
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Claims

1. Multimedia interface, comprising:

an intergrated circuit (IC) chip;

a block of reconfigurable logic incorporated on the IC chip; and

a block of media processor with a virtual instruction set capable of implementing a variety of multimedia algorithms incorporated on the IC chip separately from the reconfigurable logic block;

wherein the block of reconfigurable logic contains a least common denomination set of instruction for operating the block of media processor.

2. The multimedia interface, according to claim 1, further comprising audio and/or video CODEC incorporated on the IC chip.

3. The multimedia interface, according to claim 1, further comprising a phase locked loop (PLL) circuitry incorporated on the IC chip.

4. The multimedia interface according to claim 1, further comprising a programmable, fast serial interface core to interface to a serial interface standard incorporated on the IC chip.

5. The multimedia interface according to claim 1, further comprising a programmable CPU interface core incorporated on the IC chip.

6. The multimedia interface according to claim 1, further comprising a programmable memory interface (PMI) core incorporated on the IC chip.

7. The multimedia interface according to claim 1, further comprising a configuration port that allows a user access to the block of reconfigurable logic from off-chip.

8. Multimedia interface, comprising:

an integrated circuit (IC) chip;

a block of reconfigurable logic incorporated on the IC chip;

a media processor block incorporated on the IC chip; and

at least one additional core selected from the group consisting of

audio and/or video CODECs for interfacing to external analog signals;

phase locked loop (PLL) circuitry to reduce skew within various blocks within the IC chip;

a programmable, fast serial interface core;

a programmable CPU interface core;

a programmable memory interface (PMI) core; and

further comprising power-down circuitry, in combination with one or more of these additional cores, incorporated on the IC chip to provide power and/or processing savings when a given one of the cores is not in use. (no change)

9. Multimedia interface according to claim 8, wherein:

the at least one additional core includes the audio and/or video CODEC; and

the power-down circuitry provides the power and/or processing savings when the audio and/or video CODEC is not in use.

10. Multimedia interface according to claim 8, wherein:

the at least one additional core includes the PLL circuitry; and

the power-down circuitry provides the power and/or processing savings when the PLL circuitry is not in use.

11. Multimedia interface according to claim 8, wherein:

the at least one additional core includes the serial interface core; and

the power-down circuitry provides the power and/or processing savings when the serial interface core is not in use.

12. Multimedia interface according to claim 11, wherein:

the serial interface core is incorporated within the reconfigurable logic block.

13. Multimedia interface according to claim 8, wherein:

the at least one additional core includes the programmable CPU interface core; and

the power-down circuitry provides the power and/or processing savings when the programmable CPU interface core is not in use.

14. Multimedia interface according to claim 13, wherein;

the programmable CPU interface core is incorporated within the reconfigurable logic block.

15. Mutimedia interface according to claim 8, wherein:

the at least one additional core includes the PMI core; and

the power-down circuitry provides the power and/or processing savings when the PMI core is not in use.

16. Multimedia interface according to claim 15, wherein:

the programmable memory interface core is incorporated within the reconfigurable logic block.

17. The multimedia interface according to claim 8, wherein the media processor has a virtual instruction set capable of implementing a variety of multimedia algorithms.

18. Signal processing interface, comprising:

an integrated circuit (IC) chip;

a block of reconfigurable logic incorporated on the IC chip;

a RISC core incorporated on the IC chip; and

at least one additional core selected from the group consisting of

audio and/or video CODEC for interfacing to external analog signals;

phase locked loop (PLL) circuitry to reduce skew within various block within the IC chip;

a programmable, fast serial interface core;

a programmable CPU interface core;

a programmable memory interface (PMI) core; and

further comprising power-down circuitry, in combination with one or more of these additional cores, incorporated on the IC chip to provide power and/or processing saving when a given one of the cores is not in use.

19. Signal processing interface according to claim 18, wherein:

the at least one additional core includes audio and/or video CODEC; and

the power-down circuitry provides the power and/or processing saving when the audio and/or video CODEC is not in use.

20. Signal processing interface according to claim 18, wherein:

the at least one additional core includes the PLL circuitry; and

the power-down circuitry provides the power and/or processing savings when the PLL circuitry is not in use.

21. Signal processing interface according to claim 18, wherein:

the at least one additional core includes the serial interface core; and

the power-down circuitry provides the power and/or processing saving when the serial interface core is not in use.

22. Signal processing interface according to claim 21, wherein:

the serial interface core is incorporated within the reconfigurable logic block.

23. Signal processing interface according to claim 18, wherein:

the at least one additional core includes the programmable CPU interface core; and

the power-down circuitry provides the power and/or processing saving when the programmable CPU interface core is not in use.

24. Signal processing interface according to claim 23, wherein:

the programmable CPU interface core is incorporated within the reconfigurable logic block.

25. Signal processing interface according to claim 18, wherein:

the at least one additional core includes the PMI core; and

the power-down circuitry provides the power and/or processing savings when the PMI core is not in use.

26. Signal processing interface according to claim 25, wherein:

the programmable memory interface core is incorporated within the reconfigurable logic block.

27. Multimedia interface, comprising:

an integrated circuit (IC) chip;

a block of reconfigurable logic incorporated on the IC chip;

a media processor block incorporated on the IC chip; and

a programmable memory interface (PMI) core incorporated on the IC chip, the PMI core communicates with off-chip memory and configures it virtually into what is optimal for an application that demands non-standard size memory.

28. Signal processing interface, comprising:

an integrated circuit (IC) chip;

a block of reconfigurable logic incorporated on the IC chip;

a RISC core incorporated on the IC chip; and

a programmable memory interface (PMI) core incorporated on the IC chip, the PMI core communicates with off-chip memory and configures it virtually into what is optimal for an application that demands non-standard size memory.