Memory mapping system and method

• US 6,810,442 B1
• Filed: 09/12/2001
• Issued: 10/26/2004
• Est. Priority Date: 08/31/1998
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Axis Systems Incorporated (Cadence Systems, Inc.)
• Inventors: Tseng, Ping-Sheng, Lin, Sharon Sheau-Pyng
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): PATEL, HETUL B
• Application Number:
  US09/954,275
• Time in Patent Office: 1,140 Days
• Field of Search: 711/202, 711/152, 711/154, 703/20, 703/27, 710/22, 710/52, 716/6
• US Class Current: 710/22
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e.g. If . . . then . . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.

Claims

1. A memory mapping system for mapping at least one memory block from at least one logic device to at least one memory device in a reconfigurable hardware unit, the reconfigurable hardware unit including a conductive connector controller, at least one logic device for modeling at least a portion of a user design in hardware where a hardware model has at least one memory block and associated user memory interface, at least one memory device, a conductive connector subsystem coupling at least one logic device, at least one memory device, and the conductive connector controller, the memory mapping system comprising:

a conductive connector driver coupled to the conductive connector subsystem;

a memory block interface coupled to the conductive connector driver, the conductive connector subsystem, and the user memory interface to handle write/read memory access between at least one logic device and at least one memory device, wherein said at least one memory device storing the memory blocks associated with the hardware model; and

an evaluation logic in each logic device coupled to the hardware model, the conductive connector driver, the memory block interface, and the conductive connector controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the conductive connector driver and the memory block interface.

2. The system of claim 1, wherein the memory block interface further comprises:

a memory converter for interfacing with the user memory interface and converting the user memory type into the type of memory of the memory device in the reconfigurable hardware unit; and

a buffer coupled to the conductive connector subsystem, the evaluation logic, and the user memory interface for receiving data from the conductive connector subsystem.

3. The system of claim 2, wherein the buffer is a double buffer.

4. The system of claim 3 wherein the double buffer further comprises:

a first flip-flop having a first data input, a first data output, and a first control input, wherein the first data input is coupled to the conductive connector subsystem for receiving data, the control input coupled to the evaluation logic for receiving evaluation control signals; and

a second flip-flop having a second data input, a second data output, and a second control input, wherein the second data input is coupled to the first data output, the second control input is coupled to the evaluation logic for receiving evaluation control signals, and the second data output is coupled to the user memory interface.

5. The system of claim 4 wherein the first flip-flop and the second flip-flop are D-type flip-flops.

6. The system of claim 5 wherein the first control input receives a read latch signal from the evaluation logic for latching data on the first data output, and the second control input receives a clock enable signal from the evaluation logic to buffer in the data on the second data input to the second data output.

7. The system of claim 2 wherein the memory converter further comprises:

a memory model for receiving memory address and control signals from the user memory interface to convert the user memory type into the type of memory of the memory device in the reconfigurable hardware unit and outputting a converted control signal and converted address to the conductive connector driver; and

an address offset unit for receiving the converted address and generating an offset address to eliminate any overlaps in memory address among the memory blocks, the offset address provided to the conductive connector driver.

8. The system of claim 1 wherein the conductive connector driver is a multiplexer having a plurality of mux inputs, a mux control input, and a mux output coupled to the conductive connector subsystem.

9. The system of claim 8 wherein the plurality of mux inputs further comprises:

a first mux input for providing data associated with DMA read transfer for the hardware-to-software data, a second mux input for providing data associated with DMA read transfer for register read data, a third mux input for data associated with the user memory interface, and a fourth mux input for data associated with memory write data.

10. The system of claim 9 wherein the mux control input further comprises a select signal for selecting among the plurality of mux inputs and an output enable signal for enabling the function of the multiplexer.

11. The system of claim 1 wherein the evaluation logic includes input control signals including an evaluation signal from the conductive connector controller to control and indicate the activation of data evaluation of at least one logic device, a shiftin signal to indicate that the logic device associated with the evaluation logic will evaluate data, and a write control signal from the memory block interface to control and indicate the activation of a write operation from the logic device to at least one memory device.

12. The system of claim 1 wherein the evaluation logic generates evaluation control signals including a shiftout signal to indicate that the logic device associated with the evaluation logic will evaluate the last memory block in the logic device, a read latch signal to the memory block interface to control the reading of data from the memory device to the logic device, conductive connector driver control signals to control the operation of the conductive connector driver, and a plurality of data evaluation signals to evaluate data in the hardware model.

13. A simulation system operating in a host computer system for simulating a behavior of a circuit, the host computer system including a central processing unit (CPU), main memory, a local conductive connector coupling the CPU to main memory and allowing communication between the CPU and main memory, and a system conductive connector, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software model of the circuit coupled to the local conductive connector;

software control logic coupled to the software model and a hardware logic element, for controlling the operation of the software model and said software control logic including

interface logic which is capable of receiving input data and a clock signal from an external process, and

clock detection logic for detecting an active edge of the clock signal and generating a trigger signal; and

said hard logic element coupled to the system conductive connector and including

a system conductive connector controller,

a hardware model conductive connector coupled to the system conductive connector controller,

at least one logic device and at least one memory device coupled to the hardware model conductive connector,

a hardware model of at least a portion of the circuit residing in at least one logic device, the hardware logic element including clock enable logic for evaluating data in the hardware model in response to the trigger signal, and

a memory mapping system for mapping at least one memory block associated with the circuit in the hardware model from at least one logic device to at least one memory device.

14. The system of claim 13 wherein the memory mapping system further comprises:

a conductive connector driver coupled to the hardware model conductive connector;

a memory block interface for each memory block, the memory block interface coupled to the conductive connector drive, the hardware model conductive connector, and the hardware model to handle write/read memory access between at least one logic device and at least one memory device, wherein said at least one memory device storing the memory blocks associated with the hardware model; and

an evaluation logic in each logic device coupled to the hardware model, the conductive connector device, the memory block interface, and the system conductive connector controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the conductive connector driver and the memory block interface.

15. The system of claim 14, wherein the memory block interface further comprises:

a memory converter for interfacing with the hardware model and converting the user memory type into the type of memory of the memory device in the hardware logic element; and

a double buffer coupled to the hardware model conductive connector, the evaluation logic, and the hardware model for receiving data from the hardware model conductive connector.

16. The system of claim 15 wherein the double buffer further comprises:

a first flip-flop having a first data input, a first data output, and a first control input, wherein the first data input is coupled to the conductive connector subsystem for receiving data, the control input coupled to the evaluation logic for receiving evaluation control signals; and

a second flip-flop having a second data input, a second data output, and a second control input, wherein the second data input is coupled to the first data output, the second control input is coupled to the evaluation logic for receiving evaluation control signals including the trigger signal, and the second data output is coupled to the user memory interface.

17. A memory mapping system for mapping at least one memory block from at least one logic device to at least one memory device in a reconfigurable hardware unit, the reconfigurable hardware unit including an interconnect controller, at least one logic device for modeling at least a portion of the user design in hardware where the hardware model has at least one memory block and associated user memory interface, at least one memory device, an interconnect subsystem coupling at least one logic device, at least one memory device, and the interconnect controller, the memory mapping system comprising:

an interconnect driver coupled to the interconnect subsystem;

a memory block interface coupled to the interconnect driver, the interconnect subsystem, and the user memory interface to handle write/read memory access between at least one logic device and at least one memory device, wherein said at least one memory device storing the memory blocks associated with the hardware model; and

an evaluation logic in each logic device coupled to the hardware model, the interconnect driver, the memory block interface, and the interconnect controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the interconnect driver and the memory block interface.

18. The system of claim 17, wherein the memory block interface further comprises:

a memory converter for interfacing with the user memory interface and converting the user memory type into the type of memory of the memory device in the reconfigurable hardware unit; and

a buffer coupled to the interconnect subsystem, the evaluation logic, and the user memory interface for receiving data from the interconnect subsystem.

19. The system of claim 18, wherein the buffer is a double buffer.

20. The system of claim 19 wherein the double buffer further comprises:

a first flip-flop having a first data input, a first data output, and a first control input, wherein the first data input is coupled to the interconnect subsystem for receiving data, the control input coupled to the evaluation logic for receiving evaluation control signals; and

a second flip-flop having a second data input, a second data output, and a second control input, wherein the second data input is coupled to the first data output, the second control input is coupled to the evaluation logic for receiving evaluation control signals, and the second data output is coupled to the user memory interface.

21. The system of claim 20 wherein the first flip-flop and the second flip-flop are D-type flip-flops.

22. The system of claim 21 wherein the first control input receives a read latch signal from the evaluation logic for latching data on the first data input, and the second control input receives a clock enable signal from the evaluation logic to buffer in the data on the second data input to the second data output.

23. The system of claim 18 wherein the memory converter further comprises:

a memory model for receiving memory address and control signals from the user memory interface to converting the user memory type into the type of memory of the memory device in the reconfigurable hardware unit and outputing a converted control signal to the interconnect driver and converted address; and

an address offset unit for receiving the converted address and generating an offset address to eliminate any overlaps in memory address among the memory blocks, the offset address provided to the interconnect driver.

24. The system of claim 17 wherein the interconnect driver is a multiplexer having a plurality of mux inputs, a mux control input, and a mux output coupled to the interconnect subsystem.

25. The system of claim 24 wherein the plurality of mux inputs further comprises:

a first mux input for providing data associated with DMA read transfer for the hardware-to-software data, a second mux intput for providing data associated with DMA read transfer for register read data, a third mux intput for data associated with the user memory interface, and a fourth mux intput for data associated with memory write data.

26. The system of claim 25 wherein the mux control input further comprises a select signal for selecting among the plurality of mux inputs and an output enable signal for enabling the function of the multiplexer.

27. The system of claim 17 wherein the evaluation logic includes input control signals including an evaluation signal from the interconnect controller to control and indicate the activation of data evaluation of at least one logic device, a shiftin signal to indicate that the logic device associated with the evaluation logic will evaluate data, and a write control signal from the memory block interface to control and indicate the activation of a write operation from the logic device to at least one memory device.

28. The system of claim 17 wherein the evaluation logic generates evaluation control signals including a shiftout signal to indicate that the logic device associated with the evaluation logic will evaluate the last memory block in the logic device, a read latch signal to the memory block interface to control the reading of data from the memory device to the logic device, interconnect driver control signals to control the operation of the interconnect driver, and a plurality of data evaluation signals to evaluate data in the hardware model.