Memory request interlock

• US 6,810,470 B1
• Filed: 08/14/2000
• Issued: 10/26/2004
• Est. Priority Date: 08/14/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: McDonnell, Glen Timothy, Wiseman, John R.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US09/638,550
• Time in Patent Office: 1,534 Days
• Field of Search: 711/158, 711/141, 711/144, 711/145, 711/146, 711/163, 711/167, 711/151, 711/152
• US Class Current: 711/163
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

A memory controller for use in a computer system. The controller has a buffer having an input configured to receive read and write requests. Each request has an associated memory address. For a selected received request, prior received requests out of a set of the received requests are determined. For each determined prior received request, that request'"'"'s memory address is compared to the selected request'"'"'s memory address to see if they match. If a match exists, the selected request is prevented from being memory executed.

Claims

1. A method for controlling execution of read and write requests to a memory in a computer system, each read request is used to execute a read of an associated memory address, each write request is used to execute a write to an associated memory address, the method comprising:

providing a buffer for holding read and write requests;

receiving and holding read and write requests within the buffer;

determining for a selected read or write request within the buffer, prior received requests out of a set of the received read and write requests;

determining matched prior received requests based on in part comparing the associated memory addresses of the determined prior received requests with the selected request'"'"'s associated memory address; and

preventing the selected request from memory execution until the determined matched requests are memory executed; and

wherein the step of determining for the selected read request comprises;

providing a read pointer, the read pointer indicating a buffer location of a next write request to be memory executed;

providing a write pointer, the write pointer indicating a buffer location of a next write request to be received by the buffer;

determining for the selected read request prior received write requests based on in part the write pointer and the read pointer location; and

providing a lock pointer, the lock pointer indicating a buffer location associated with the write pointer when the selected read request is received; and

the determining of prior received write requests is based on in part the write pointer, the read pointer and lock pointer location.

2. The method of claim 1 wherein the step of determining prior received requests comprises:

time stamping each received request at reception; and

determining for the selected read or write request within the buffer, the prior received requests based on in part the prior received requests'"'"' time stamps.

3. The method of claim 1 wherein the selected request is a read request and the set of received requests are all of the received write requests.

4. The method of claim 1 wherein the step of determining for the selected read request further comprises:

providing a status flag, the status flag indicating whether the buffer is full; and

the determining of prior received write requests is based on in part the write pointer location, the read pointer location, the lock pointer location and the status flag.

5. The method of claim 1 wherein the selected request is a write request and the set of received requests are all of the received read requests.

6. The method of claim 5 wherein the step of determining for the selected write request comprises:

providing a read pointer, the read pointer indicating a buffer location of a next read request to be memory executed;

providing a write pointer, the write pointer indicating a buffer location of a next read request to be received by the buffer; and

determining for the selected write request prior received read requests based on in part the write pointer and the read pointer location.

7. The method of claim 6 wherein the step of determining for the selected write request further comprises:

providing a lock pointer, the lock pointer indicating a buffer location associated with the write pointer when the selected write request is received; and

the determining of prior received read requests is based on in part the write pointer, the read pointer and the lock pointer location.

8. The method of claim 7 wherein the step of determining for the selected write request further comprises:

providing a status flag, the status flag indicating whether the buffer is full; and

the determining of prior received read requests is based on in part the write pointer location, the read pointer location, the lock pointer location and the status flag.

9. The method of claim 1 wherein the selected request is a write request and the set of received requests are other received write requests.

10. The method of claim 1 wherein a requesting clients and a arbiter are operating at different clocking rates, the method further comprising synchronizing a client requests to a arbiter clock domain.

11. A memory controller for use in a computer system, the memory controller comprising:

a buffer having an input configured to receive read and write requests and for holding the received read and write requests, each read request is used to execute a read of an associated memory address and each write request is used to execute a write to an associated memory address;

a lock maintenance device for determining for a selected received read or write request prior received requests out of a set of the received read and write requests and for preventing the selected request from being sent to an arbiter until determined matched requests are sent to the arbiter;

a coherency test device for determining the determined matched requests based on in part comparing the associated memory addresses of the determined prior received requests with the selected request'"'"'s associated memory address; and

the arbiter for selecting from the held read and write requests in the buffer a next request for memory execution;

wherein the selected request is a write request and the set of received requests are all of the received read requests.

12. The memory controller of claim 11 further comprising a sequencer operatively coupled to the arbiter, the sequencer for executing the read and write requests selected by the arbiter.

13. A memory controller for use in a computer system, the memory controller comprising:

a buffer having an input configured to receive read and write requests and for holding the received read and write requests, each read request is used to execute a read of an associated memory address and each write request is used to execute a write to an associated memory address;

a lock maintenance device for determining for a selected received read or write request prior received requests out of a set of the received read and write requests and for preventing the selected request from being sent to an arbiter until determined matched requests are sent to the arbiter;

a coherency test device for determining the determined matched requests based on in part comparing the associated memory addresses of the determined prior received requests with the selected request'"'"'s associated memory address; and

the arbiter for selecting from the held read and write requests in the buffer a next request for memory execution;

wherein the selected request is a write request and the set of received requests are other received write requests.