Method and apparatus of programmable interconnect array with configurable multiplexer

• US 6,810,513 B1
• Filed: 06/19/2002
• Issued: 10/26/2004
• Est. Priority Date: 06/19/2002
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Vest, William Bradley
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US10/175,264
• Time in Patent Office: 860 Days
• Field of Search: 716/16, 716/12, 716/13, 716/14
• US Class Current: 326/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A method and an apparatus for routing various signals within an integrated circuit is disclosed. In one embodiment, the integrated circuit is a programmable logic device, wherein it includes a logic block, a control block, and a routing block. Each logic block further includes multiple logical array blocks so that logical array blocks can be configured to perform specific logic functions. The routing block includes a first and second routing arrays, wherein each routing array has at least one configurable multiplexer and one output circuit. The configurable multiplexer of the first routing array can be programmed to route a signal through the output circuit of the second routing array.

Claims

1. An integrated circuit (“

IC”

) device comprising;

a first routing array (“

RA”

), the first RA having a configurable multiplexer, the configurable multiplexer having at least two outputs, and one output circuit, wherein one output of the configurable multiplexer of the first RA is coupled with the output circuit of the first RA;

a second RA, having at least one configurable multiplexer and one output circuit, coupled to the first RA, wherein at least one output of the configurable multiplexer of the first RA is programmed to couple to the output circuit of the second RA; and

a logic block, having a configurable element, coupled to the first and second RAs, wherein the configurable multiplexer of the first RA routes a signal to the logic block via the output circuit of the second RA.

2. The IC device of claim 1 further comprises:

a first set of routing wires coupled to the first RA, the first set of routing wires configured to receive a first group of input data and to transmit the first group of input data to the first RA; and

a second set of routing wires coupled to the second RA, the second set of routing wires configured to receive a second group of input data and to transmit the second group of input data to the second RA.

3. The IC device of claim 2, wherein the logic block is a programmable logic circuit capable of performing various product-term logical functions.

4. The IC device of claim 3, wherein the configurable multiplexer of the first RA routes another signal to the logic block via the output circuit of the first RA.

5. The IC device of claim 4, wherein the input data includes signals from input/output pins, input pins, and feedback paths.

6. The IC device of claim 5, wherein the signal to the logic block via the output circuit of the second RA is from the first group of input data.

7. The IC device of claim 6, wherein the signal to the logic block via the output circuit of the first RA is from the first group of input data.

8. The IC device of claim 1, wherein the first RA includes nine configurable multiplexers and wherein the second RA includes nine configurable multiplexers.

9. The IC device of claim 1, wherein the output circuit of the first RA is part of the configurable multiplexer of the first RA and the output circuit of the second RA is a part of the configurable multiplexer of the second RA.

10. The IC device of claim 9, wherein the configurable multiplexer is programmable to function as one of a 4-to-1 multiplexer and 4-to-2 multiplexer.

11. A device comprising:

a first set of routing channels configured to transmit a first input data;

a first configurable interconnect array, having a plurality of first routing blocks, coupled to the first set of routing channels, wherein each of the first routing blocks includes a first selecting circuit and a first output circuit;

a second set of routing channels configured to transmit second input data;

a second configurable interconnect array, having a plurality of second routing blocks, coupled to the second set of routing channels, wherein each of the plurality of second routing blocks includes a second selecting circuit and a second output circuit; and

a logic block, having a configurable element, coupled to the first and second configurable interconnect arrays, wherein one of the first selecting circuit of the plurality of the first routing blocks transmits a first signal of the first input data to the logic block via one of the second output circuit of the plurality of second routing blocks.

12. The device of claim 11, wherein the first selecting circuit further transmits a second signal of the first input data to the logic block via the first output circuit.

13. The device of claim 12, wherein the first selecting circuit is programmed to coupled to the second output circuit.

14. The device of claim 12, wherein the first selecting circuit is programmed to coupled to the first output circuit.

15. The device of claim 11, wherein the first selecting circuit is configurable to a 4-to-1 multiplexer or a 4-to-2 multiplexer.

16. A digital processing system comprising:

a processor;

a memory coupled to the processor; and

a circuit as defined in claim 11 coupled to the processor and memory.

17. A printed circuit board on which is mounted an integrated circuit as defined in claim 11.

18. The printed circuit board of claim 17, further comprising:

a memory mounted on the printed circuit board and coupled to the integrated circuit; and

a processor mounted on the printed circuit board and coupled to the memory.

19. A method of routing signals in an integrated circuit, comprising:

programming a first configurable multiplexer having at least two outputs to connect a first output of the first configurable multiplexer in a first routing array (“

RA”

) to an input of a output circuit in a second RA;

receiving a first set of signals from a first set of routing wires;

selecting a first signal from the first set of signals; and

transmitting the first signal to a logic block via the second output circuit.

20. The method of claim 19 further comprising:

selecting a second signal from the first set of signals in response to first control signals; and

transmitting the second signal to said logic block via a first output circuit in the first RA.

21. The method of claim 20, wherein the programming to connect a first output of a first configurable multiplexer in a first RA to an input of a second output circuit in a second RA further includes:

programming the first configurable multiplexer; and

programming the second output circuit.

22. The method of claim 21, wherein the programming the first configurable multiplexer includes configuring the first configurable multiplexer to function as two 2- to-1 multiplexers.

23. The method of claim 21, wherein the programming the second output circuit includes:

programming to logically disconnect the second output circuit from a second configurable multiplexer in the second RA; and

programming to logically connect the second output circuit to the first configurable multiplexer.

24. An apparatus for routing signals in an integrated circuit, comprising:

means for selecting a first circuit to transmit a first input signal to a programmable logic block;

means for selecting a second circuit to transmit the first input signal to the programmable logic block when the first circuit is busy; and

means for selecting a third circuit to transmit the first input signal to the programmable logic block when the first and second circuits are busy.

25. The apparatus of claim 24 further comprising:

means for selecting the second circuit to transmit a second input signal to the programmable logic block;

means for selecting the first circuit to transmit the second input signal to the programmable logic block when the second circuit is busy; and

means for selecting a fourth circuit to transmit the second input signal to the programmable logic block when the first and second circuits are busy.

26. The apparatus of claim 24, wherein the means for selecting a first circuit to transmit a first input signal to a programmable logic block further includes:

means for generating a first output signal in response to the first input signal;

means for buffering the first output signal; and

means for transmitting the first output signal to the programmable logic block via a bus.

27. The apparatus for claim 24, wherein the means for transmitting the first output signal to the programmable logic block via a bus further includes:

means for identifying a plurality conductors within the bus;

means for selecting a first conductor that connects to the programmable logic block; and

means for transmitting the first output signal to the programmable logic block over the first conductor.

28. The apparatus of claim 24, wherein the means for selecting a second circuit to transmit the first input signal to the programmable logic block when the first circuit is busy further includes:

means for identifying whether the first circuit is assigned to select the first input signal as its output signal; and

means for indicating the first circuit is busy when the first circuit does not select the first input signal as its output signal.

29. A device comprising:

a first configurable multiplexer; and

a control circuit coupled to the first configurable multiplexer, the control circuit selectively programming the first configurable multiplexer to be one of 6-to-1, 4-to-1, and 2-to-1 multiplexers.

30. The device of claim 29 further comprising:

a first output circuit coupled to the first configurable multiplexer;

a second output circuit coupled to a second configurable multiplexer; and

a logic block, having a configurable element, coupled to the first and second configurable multiplexers, wherein the first configurable multiplexer routes a signal to the logic block via second output circuit.

31. The device of claim 29, wherein the control circuit selectively program the first configurable multiplexer to be a 4-to-1 multiplexer.

32. The device of claim 29, wherein the control circuit selectively programs the first configurable multiplexer to be two 2-to-1 multiplexers.