Pre-cleaning for silicidation in an SMOS process

• US 6,811,448 B1
• Filed: 07/15/2003
• Issued: 11/02/2004
• Est. Priority Date: 07/15/2003
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Paton, Eric N., Besser, Paul R., Xiang, Qi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/619,879
• Time in Patent Office: 476 Days
• Field of Search: 438/751, 438/752, 438/706
• US Class Current: 439/706
• CPC Class Codes: H01L 21/02046 Dry cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02054 combining dry and wet cleaning steps H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

Claims

1. A method of manufacturing an integrated circuit comprising:

providing a substrate, the substrate including a layer including germanium;

providing a gate structure above the substrate;

pre-cleaning the substrate using hydrofluoric acid after the step of providing a gate structure; and

pre-cleaning the substrate with an argon and hydrogen plasma after the step of pre-cleaning the substrate using hydrofluoric acid; and

siliciding the substrate.

2. The method of claim 1, wherein the step of pre-cleaning the substrate using hydrofluoric acid removes thermal oxide from the substrate and the step of pre-cleaning the substrate using an argon and hydrogen plasma removes thermal oxide remaining after the step of pre-cleaning the substrate using hydrofluoric acid.

3. The method of claim 1, wherein the step of pre-cleaning the substrate using an argon and hydrogen plasma utilizes a total gas pressure of approximately 100 Pa and a hydrogen flow rate of approximately 100 sccm.

4. The method of claim 1, wherein the step of pre-cleaning the substrate using hydrofluoric acid comprises exposing the substrate to a wet bath.

5. The method of claim 1, wherein the gate structure includes a polysilicon conductor.

6. The method of claim 5, wherein the polysilicon conductor is pre-cleaned and silicided.

7. A method of pre-cleaning a top surface of an IC substrate before silicidation in a chamber, the method comprising:

exposing the IC substrate to hydrofluoric acid to remove native oxide from the IC substrate; and

providing a plasma including hydrogen in the chamber to remove native oxide from the IC substrate remaining after the exposure of the IC substrate to hydrofluoric acid.

8. The method of claim 7, wherein the step of exposing the IC substrate to hydrofluoric acid comprises providing a wet bath to reduce a thickness of the native oxide.

9. The method of claim 8, wherein the wet bath utilizes hydrofluoric acid and water.

10. The method of claim 8, wherein the chamber is a vacuum chamber and a metal layer is deposited on the IC substrate in the chamber after the after the steps of exposing the IC substrate to hydrofluoric acid and providing a plasma including hydrogen in the chamber.

11. The method of claim 10, wherein the thickness of the native oxide on the IC substrate is eliminated using the wet bath.

12. The method of claim 7, further comprising providing a silicide layer.

13. The method of claim 7, further comprising evacuating the chamber.

14. The method of claim 7, wherein the plasma includes argon.

15. The method of claim 7, wherein the IC substrate includes a germanium containing gate conductor.

16. The method of claim 7, wherein the chamber is part of a deposition tool.

17. A method of manufacturing a transistor on an integrated circuit, the method comprising:

providing a gate structure on a top surface of a strained silicon layer or a silicon germanium layer;

removing a native oxide material from the strained silicon layer or silicon germanium layer using a hydrofluoric acid wet bath;

providing a plasma including hydrogen and argon to remove the native oxide material; and

siliciding the top surface.

18. The method of claim 17, further comprising utilizing hydrofluoric acid to remove a portion of the native oxide material before providing the plasma including hydrogen and argon.

19. The method of claim 18, wherein the siliciding is a nickel siliciding process.

20. The method of claim 19, wherein the top surface includes a silicon/germanium gate conductor.