Field programmable logic arrays with vertical transistors

• US 6,812,516 B2
• Filed: 08/28/2002
• Issued: 11/02/2004
• Est. Priority Date: 02/27/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/230,244
• Publication Number:
  US 20020195649A1
• Time in Patent Office: 797 Days
• Field of Search: 257/315, 257/314, 257/316, 257/317, 257/319, 257/320, 257/329, 257/321, 257/390, 257/318
• US Class Current: 257/315
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F² is needed per bit of logic, where F is the minimum lithographic feature size.

Claims

1. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a floating gate, substantially adjacent to only a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a split control line, substantially adjacent to the floating gate and insulated therefrom, wherein there are two control lines between two common pillars; and

an intergate dielectric, interposed between the floating gate and the control lines, and between the two control lines.

2. The floating gate transistor of claim 1, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

3. The floating gate transistor of claim 1, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

4. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a floating gate, substantially adjacent to only a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, substantially adjacent to the floating gate and insulated therefrom, wherein the single control line is associated with a pair of adjacent pillars; and

an intergate dielectric, interposed between the floating gates and the single control line.

5. The logic cell of claim 4, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

6. The logic cell of claim 4, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

7. The logic cell of claim 4, wherein at least a pair of floating gates are formed substantially adjacent to two opposing side surfaces of the pillar.

8. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a floating gate, substantially adjacent to only a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, substantially adjacent to the floating gate and insulated therefrom, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the single control line; and

a source line located adjacent to the first source/drain region.

9. The logic cell of claim 8, wherein the source line is disposed, at least partially within the substrate.

10. The logic cell of claim 9, wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by ion implantation.

11. The logic cell of claim 9, wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by diffusing dopants into the substrate.

12. The logic cell of claim 8, wherein the source line is located beneath the pillar.

13. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a plurality of floating gates, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, wherein the single control line is associated with control gates on a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gate and the single control line; and

a source line disposed, at least partially within the substrate, the source line being located adjacent to the first source/drain region.

14. The logic cell of claim 13, wherein the source line is located beneath the pillar.

15. The logic cell of claim 13, wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by ion implantation.

16. The logic cell of claim 13, wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by diffusing dopants into the substrate.

17. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars; and

an intergate dielectric, interposed between the floating gates and the single control line.

18. The logic cell of claim 17, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

19. The logic cell of claim 17, wherein a pitch between control lines on opposite sides of the pillar is approximately twice a minimum lithographic feature size.

20. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the two control lines; and

a source line located adjacent to the first source/drain region.

21. The logic cell of claim 20, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

22. The logic cell of claim 20, wherein the source line is disposed, at least partially within the substrate.

23. A logic cell, comprising:

an AND plane and an OR plane operatively coupled together;

a floating gate transistor that is fabricated upon a substrate, the transistor including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the two control lines; and

a source line disposed, at least partially within the substrate, the source line being located adjacent to the first source/drain region.

24. The logic cell of claim 23, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

25. The logic cell of claim 23, wherein the source line is located beneath the pillar.