System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits
First Claim
Patent Images
1. A compensation circuit for an adjustable delay circuit having fine and coarse delay circuits, comprising:
- a reference delay circuit having an input at which an input clock signal is applied and an output at which a reference delayed clock signal is provided, the reference delay circuit having a reference fine delay component and a reference coarse delay component, the time delay of the coarse delay component greater than the time delay of the fine delay component and having an expected relationship with respect to the time delay of the fine delay component;
an adjustable fine delay circuit having a control terminal at which a control signal is applied, and further having an input at which the input clock signal is applied and an output at which a variable delayed clock signal is provided, the adjustable fine delay circuit having a time delay adjusted according to the control signal;
a phase detector having a first input coupled to the output of the reference coarse delay component and a second input coupled to the output of the adjustable fine delay circuit to compare the phase relationship of the reference delayed clock signal and the variable delayed clock signal, the phase detector generating an output signal indicative of the phase relationship;
a feedback circuit coupled to the phase detector to generate a compensation signal indicative of the variance from the expected relationship between the time delay of the coarse and fine delay components based on the output signal from the phase detector; and
a stabilization circuit coupled to the feedback circuit and the adjustable fine delay circuit and configured to generate a stabilized compensation signal provided to the adjustable fine delay circuit as the control signal in response to the compensation signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate.
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Abstract
A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.
86 Citations
46 Claims
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1. A compensation circuit for an adjustable delay circuit having fine and coarse delay circuits, comprising:
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a reference delay circuit having an input at which an input clock signal is applied and an output at which a reference delayed clock signal is provided, the reference delay circuit having a reference fine delay component and a reference coarse delay component, the time delay of the coarse delay component greater than the time delay of the fine delay component and having an expected relationship with respect to the time delay of the fine delay component;
an adjustable fine delay circuit having a control terminal at which a control signal is applied, and further having an input at which the input clock signal is applied and an output at which a variable delayed clock signal is provided, the adjustable fine delay circuit having a time delay adjusted according to the control signal;
a phase detector having a first input coupled to the output of the reference coarse delay component and a second input coupled to the output of the adjustable fine delay circuit to compare the phase relationship of the reference delayed clock signal and the variable delayed clock signal, the phase detector generating an output signal indicative of the phase relationship;
a feedback circuit coupled to the phase detector to generate a compensation signal indicative of the variance from the expected relationship between the time delay of the coarse and fine delay components based on the output signal from the phase detector; and
a stabilization circuit coupled to the feedback circuit and the adjustable fine delay circuit and configured to generate a stabilized compensation signal provided to the adjustable fine delay circuit as the control signal in response to the compensation signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a latch having inputs coupled to the output of the reference delay circuit and the adjustable fine delay circuit, and further having outputs; and
a buffer circuit coupled to the outputs of the latch to provide an output signal having first and second components to the feedback circuit.
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5. The compensation circuit of claim 1 wherein the coarse delay component of the reference delay circuit comprises a pair of series coupled inverters.
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6. The compensation circuit of claim 1 wherein the reference fine delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference coarse delay component.
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7. The compensation circuit of claim 1 wherein the reference coarse delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference fine delay component.
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8. A compensation circuit for a variable delay circuit, comprising:
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an adjustable delay stage having a control input at which a control signal is applied, an input at which a clock signal is applied, and an output at which a variable delay clock signal is provided, the adjustable delay stage having a variable delay adjusted according to the control signal;
a first reference delay stage having an input at which the clock signal is applied and an output at which a delayed clock signal is provided, the first reference delay stage having a first reference time delay;
a second reference delay stage coupled to the first reference delay stage and having an output at which a reference delay clock signal is provided, the second reference delay stage having a second reference time delay with an expected delay relationship to the first reference time delay;
a latch circuit having a first input coupled to the second reference delay stage and a second input coupled to the adjustable delay stage to compare the phase relationship between the reference delay clock signal and the variable delay clock signal, the latch circuit further having first and second outputs at which first and second phase signals indicative of the phase relationship are provided, respectively;
a feedback circuit coupled to the first and second outputs of the latch circuit to generate a feedback signal in response to the logic states of the first and second phase signals, the feedback signal indicative of the variance from the expected delay relationship and provided by the feedback circuit to the adjustable delay stage as the control signal; and
a signal stabilization circuit coupled to the feedback circuit and configured to generate a stabilized feedback signal as the control signal in response to the feedback signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate. - View Dependent Claims (9, 10, 11, 12, 13)
an S-R latch having inputs coupled to the second reference delay stage and the adjustable delay circuit; and
a buffer circuit coupled to outputs of the S-R latch to provide an output signal having first and second components to the feedback circuit.
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12. The compensation circuit of claim 8 wherein the first reference delay stage comprises a reference fine delay stage and the second reference delay stage comprises a reference coarse delay stage.
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13. The compensation circuit of claim 8 wherein the first reference delay stage comprises a reference coarse delay stage and the second reference delay stage comprises a reference fine delay stage.
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14. A delay-locked loop, comprising:
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a variable delay line having a fine delay circuit and at least one coarse delay circuit;
a delay controller coupled to the variable delay line for adjusting the time delay of the variable delay line; and
a compensation circuit coupled to the delay controller for adjusting a time delay relationship between the fine delay and the coarse delay circuits of the variable delay line, the compensation circuit comprising, a reference delay circuit having an input at which an input clock signal is applied and an output at which a reference delayed clock signal is provided, the reference delay circuit having a reference fine delay component and a reference coarse delay component, the time delay of the coarse delay component greater than the time delay of the fine delay component and having an expected relationship with respect to the time delay of the fine delay component;
an adjustable fine delay circuit having a control terminal at which a control signal is applied, and further having an input at which the input clock signal is applied and an output at which a variable delayed clock signal is provided, the adjustable fine delay circuit having a time delay adjusted according to the control signal;
a phase detector having a first input coupled to the output of the reference coarse delay component and a second input coupled to the output of the adjustable fine delay circuit to compare the phase relationship of the reference delayed clock signal and the variable delayed clock signal, the phase detector generating an output signal indicative of the phase relationship;
a feedback circuit coupled to the phase detector to generate a compensation signal indicative of the variance from the expected relationship between the time delay of the coarse and fine delay components based on the output signal from the phase detector; and
a stabilization circuit coupled to the feedback circuit and the adjustable fine delay circuit and configured to generate a stabilized compensation signal provided to the adjustable fine delay circuit as the control signal in response to the compensation signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate. - View Dependent Claims (15, 16, 17, 18, 19, 20)
a latch having inputs coupled to the output of the reference delay circuit and the adjustable fine delay circuit, and further having outputs; and
a buffer circuit coupled to the outputs of the latch to provide an output signal having first and second components to the feedback circuit.
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18. The delay-locked loop of claim 14 wherein the coarse delay component of the reference delay circuit comprises a pair of series coupled inverters.
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19. The delay-locked loop of claim 14 wherein the reference fine delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference coarse delay component.
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20. The delay-locked loop of claim 14 wherein the reference coarse delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference fine delay component.
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21. A memory device, comprising:
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an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the data bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and
a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising, a variable delay line having a fine delay circuit and at least one coarse delay circuit;
a delay controller coupled to the variable delay line for adjusting the time delay of the variable delay line; and
a compensation circuit coupled to the delay controller for adjusting a time delay relationship between the fine delay and the coarse delay circuits of the variable delay line, the compensation circuit comprising, a reference delay circuit having an input at which the input clock signal is applied and an output at which a reference delayed clock signal is provided, the reference delay circuit having a reference fine delay component and a reference coarse delay component, the time delay of the coarse delay component greater than the time delay of the fine delay component and having an expected relationship with respect to the time delay of the fine delay component;
an adjustable fine delay circuit having a control terminal at which a control signal is applied, and further having an input at which the input clock signal is applied and an output at which a variable delayed clock signal is provided, the adjustable fine delay circuit having a time delay adjusted according to the control signal;
a phase detector having a first input coupled to the output of the reference coarse delay component and a second input coupled to the output of the adjustable fine delay circuit to compare the phase relationship of the reference delayed clock signal and the variable delayed clock signal, the phase detector generating an output signal indicative of the phase relationship; and
a feedback circuit coupled to the phase detector to generate a compensation signal indicative of the variance from the expected relationship between the time delay of the coarse and fine delay components based on the output signal from the phase detector, the feedback circuit further providing the compensation signal to the adjustable fine delay circuit as the control signal; and
a stabilization circuit coupled to the feedback circuit and the adjustable fine delay circuit and configured to generate a stabilized compensation signal provided to the adjustable fine delay circuit as the control signal in response to the compensation signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate. - View Dependent Claims (22, 23, 24, 25, 26, 27)
a latch having inputs coupled to the output of the reference delay circuit and the adjustable fine delay circuit, and further having outputs; and
a buffer circuit coupled to the outputs of the latch to provide an output signal having first and second components to the feedback circuit.
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25. The memory device of claim 21 wherein the coarse delay component of the reference delay circuit comprises a pair of series coupled inverters.
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26. The memory device of claim 21 wherein the reference fine delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference coarse delay component.
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27. The memory device of claim 21 wherein the reference coarse delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference fine delay component.
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28. A computer system, comprising:
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a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a memory device coupled to the processor, the memory device comprising, an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the data bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and
a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising, a variable delay line having a fine delay circuit and at least one coarse delay circuit;
a delay controller coupled to the variable delay line for adjusting the time delay of the variable delay line; and
a compensation circuit coupled to the delay controller for adjusting a time delay relationship between the fine delay and the coarse delay circuits of the variable delay line, the compensation circuit comprising, a reference delay circuit having an input at which the input clock signal is applied and an output at which a reference delayed clock signal is provided, the reference delay circuit having a reference fine delay component and a reference coarse delay component, the time delay of the coarse delay component greater than the time delay of the fine delay component and having an expected relationship with respect to the time delay of the fine delay component;
an adjustable fine delay circuit having a control terminal at which a control signal is applied, and further having an input at which the input clock signal is applied and an output at which a variable delayed clock signal is provided, the adjustable fine delay circuit having a time delay adjusted according to the control signal;
a phase detector having a first input coupled to the output of the coarse delay circuit and a second input coupled to the output of the adjustable fine delay circuit to compare the phase relationship of the reference delayed clock signal and the variable delayed clock signal, the phase detector generating an output signal indicative of the phase relationship;
a feedback circuit coupled to the phase detector to generate a compensation signal indicative of the variance from the expected relationship between the time delay of the coarse and fine delay components based on the output signal from the phase detector, the feedback circuit further providing the compensation signal to the adjustable fine delay circuit as the control signal; and
a stabilization circuit coupled to the feedback circuit and the adjustable fine delay circuit and configured to generate a stabilized compensation signal provided to the adjustable fine delay circuit as the control signal in response to the compensation signal from the feedback circuit, the stabilization circuit including at least one stabilization stage having a flip-flop coupled to an input of a NOR gate and an inverter coupled to the output of the NOR gate. - View Dependent Claims (29, 30, 31, 32, 33, 34)
a latch having inputs coupled to the output of the reference delay circuit and the adjustable fine delay circuit, and further having outputs; and
a buffer circuit coupled to the outputs of the latch to provide an output signal having first and second components to the feedback circuit.
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32. The computer system of claim 28 wherein the coarse delay component of the reference delay circuit comprises a pair of series coupled inverters.
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33. The computer system of claim 28 wherein the reference fine delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference coarse delay component.
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34. The computer system of claim 28 wherein the reference coarse delay component of the reference delay circuit is coupled to receive the input clock signal and provide an output clock signal to the reference fine delay component.
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35. A method for compensating for variance from an expected relationship between a fine delay circuit and a coarse delay circuit of a variable delay line, the method comprising:
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delaying an input clock signal by a reference time delay to generate a reference delay clock signal, the reference time delay having a reference fine time delay component and a reference coarse time delay component;
delaying the input clock signal by an adjustable time delay to generate a variable delay clock signal, the adjustable time delay greater than or equal to the reference fine time delay component and less than the reference coarse time delay component;
generating a phase signal indicative of the phase relationship between the reference delay clock signal and the variable delay clock signal;
generating a feedback signal responsive to the phase signal that is indicative of the variance from the expected relationship between the fine delay circuit and the coarse delay circuit;
stabilizing the feedback signal by ignoring transitions of the feedback signal occurring within at least one period of the input clock signal;
adjusting the adjustable time delay according to the stabilized feedback signal to synchronize the phase of the reference delay clock signal and the variable delay clock signal; and
adjusting the relationship between the fine delay circuit and the coarse delay circuit according to the stabilized feedback signal at phase lock. - View Dependent Claims (36, 37, 38, 39, 40)
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41. A method for compensating for variance from an expected relationship between a fine delay circuit and a coarse delay circuit of a variable delay line, the method comprising:
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determining the phase relationship between a reference delay clock signal delayed from an input clock signal by reference time delay and an adjustable delay clock signal delayed from the input clock signal by an adjustable time delay, the reference time delay having a reference fine delay component and a reference coarse delay component;
generating a compensation signal based on the phase relationship between the reference delay clock signal and the adjustable delay clock signal;
stabilizing the compensation signal by ignoring transitions of the compensation signal occurring within at least one period of the input clock signal;
adjusting the adjustable time delay to correct for the phase difference between the reference delay clock signal and the adjustable delay clock signal responsive to the stabilized compensation signal; and
setting the point at which the variable delay line switches from a fine delay circuit to a coarse delay circuit based on the stabilized compensation signal at phase lock to compensate for the variance from the expected relationship. - View Dependent Claims (42, 43, 44, 45, 46)
delaying the input clock signal by a reference time delay to generate the reference delay clock signal;
delaying the input clock signal by an adjustable time delay to generate the variable delay clock signal; and
generating a phase signal indicative of the phase relationship between the reference delay clock signal and the variable delay clock signal.
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44. The method of claim 43 wherein delaying the input clock signal a reference time delay comprises delaying the input clock signal by the reference fine time delay component before delaying the input clock signal by the reference coarse time delay component.
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45. The method of claim 43 wherein delaying the input clock signal a reference time delay comprises delaying the input clock signal by the reference coarse time delay component before delaying the input clock signal by the reference fine time delay component.
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46. The method of claim 43 wherein generating a phase signal comprises generating a phase signal having an up-shift signal and a down-shift signal and wherein generating the compensation signal comprises modifying a binary value by shifting bits according to the up and down shift signals of the phase signal.
Specification