Interrupt method, system and medium

• US 6,813,665 B2
• Filed: 09/21/2001
• Issued: 11/02/2004
• Est. Priority Date: 09/21/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kulick, Stanley S., Cekleov, Michael, Rankin, Linda J.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/962,720
• Publication Number:
  US 20030061423A1
• Time in Patent Office: 1,138 Days
• Field of Search: 710/48, 710/260, 710/262, 710/264, 710/266, 710/268
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

An interrupt method, system, and/or medium may comprise generating a load balancing value that helps balance servicing of interrupts among processors.

Claims

1. A system comprising

a processor set;

an I/O device to generate an interrupt;

an input/output (I/O) subsystem to generate an interrupt message comprising a load balancing value in response to the interrupt of the I/O device; and

a node controller to determine, based at least upon the load balancing value of the interrupt message, whether at least one processor of the processor set is to process the interrupt.

2. The system of claim 1, wherein the node controller causes at least one processor of the processor set to process the interrupt in response to determining that at least one processor of the plurality of processors is to process the interrupt.

3. The system of claim 1, further comprising

another processor set; and

another node controller to cause at least one processor of the another processor set to process the interrupt in response to determining based at least upon the load balancing value of the interrupt message that at least one processor of the another processor set is to process the interrupt.

4. The system of claim 1, wherein the I/O subsystem updates the load balancing value in response to receiving the interrupt.

5. The system of claim 1, wherein the I/O subsystem generates the interrupt message such that the interrupt message comprises a destination identifier that identifies processors suitable for processing the interrupt.

6. The system of claim 1, wherein

the I/O subsystem generates the interrupt message such that the interrupt message comprises a destination identifier that identifies processors suitable for processing the interrupt, and

the node controller identifies a default processor for the interrupt based upon the destination identifier and to cause at least one processor of the processor set to process the interrupt in response to determining that the processor set comprises the default processor.

7. A method comprising

generating an interrupt message comprising a load balancing value in response to an interrupt.

8. The method of claim 7, further comprising

updating the load balancing value in response to the interrupt.

9. The method of claim 7, further comprising

updating the load balancing value in accordance with a predetermined load balancing algorithm.

10. The method of claim 7, further comprising

updating the load balancing value in accordance with a wrap-around counter algorithm.

11. The method of claim 7, wherein generating further comprises

generating the interrupt message to further comprise a destination identifier that identifies one or more targets suitable for processing the interrupt.

12. The method of claim 7, further comprising

causing at least one processor of a processor set to process the interrupt in response to determining, based at least upon the load balancing value of the interrupt message, that at least one processor of the processor set is to process the interrupt.

13. The method of claim 7, further comprising

generating the interrupt message to further comprise a destination identifier that identifies one or more targets suitable for processing the interrupt;

identifying a default processor for the interrupt based at least upon the destination identifier and load balancing value; and

causing at least one processor of a processor set to process the interrupt in response to the processor set comprising the default processor.

14. The method of claim 7, further comprising

generating the interrupt message to further comprise a destination identifier that identifies one or more targets suitable for processing the interrupt;

identifying a default processor for the interrupt based at least upon the destination identifier and the load balancing value; and

selecting a lowest priority processor of the processor set to process the interrupt in response to the processor set comprising the default processor.

15. A method comprising

determining, based at least upon a load balancing value of an interrupt message, whether at least one processor of a processor set is to process an interrupt associated with the interrupt message.

16. The method of claim 15, further comprising

causing at least one processor of the processor set to process the interrupt in response to determining that at least one processor of the processor set is to process the interrupt.

17. The method of claim 15, further comprising

providing at least one processor of the processor set with an updated interrupt message comprising an identifier that identifies at least one processor of the processor set in response to determining that at least one processor of the processor set is to process the interrupt.

18. The method of claim 15, wherein determining further comprises

identifying a default processor for the interrupt based at least upon the load balancing value and a destination identifier of the interrupt message that identifies one or more processors suitable to process the interrupt;

and

determining that at least one processor of the processor set is to process the interrupt in response to the processor set comprising the default processor.

19. The method of claim 15, wherein determining further comprises identifying a default processor for the interrupt based at least upon the load balancing value and a destination identifier of the interrupt message that identifies one or more processors suitable to process the interrupt, and the method further comprises

selecting a lowest priority processor of the processor set identified by the destination identifier to process the interrupt in response to the processor set comprising the default processor.

20. The method of claim 15, wherein determining further comprises

applying a first find algorithm to the destination identifier of the interrupt message to obtain a default processor for the interrupt, a starting position of the first find algorithm being based at least in part upon the load balancing value of the interrupt message, and

determining that at least one processor of the processor set is to process the interrupt in response to the processor set comprising the default processor.

21. The method of claim 15, wherein determining further comprises

applying a first find algorithm to a destination identifier of the interrupt message to obtain a default processor for the interrupt, a starting position of the first find algorithm being based at least in part upon the load balancing value of the interrupt message, and

selecting a lowest priority processor of the processor set identified by the destination identifier to process the interrupt in response to the processor set comprising the default processor.

22. A machine-readable medium, comprising a plurality of instructions, which in response to being executed, result in an interrupt controller

identifying a default processor to service an interrupt based at least upon a load balancing value and a destination identifier that identifies a target processor set to service the interrupt;

determining based upon the default processor whether a node processor set associated with the interrupt controller is to service the interrupt

identifying a node target processor set comprising processors that are enabled for servicing interrupts, that are included in the target processor set and that are included in the node processor set; and

selecting a processor to service the interrupt from the node target processor set in response to determining that the node processor set is to service the interrupt.

23. The machine-readable medium of claim 22, wherein the plurality of instructions, in response to being executed, further result in the interrupt controller

providing the selected processor with an updated interrupt message comprising an identifier that identifies the selected processor to service the interrupt.

24. The machine-readable medium of claim 22, wherein the plurality of instructions, in response to being executed, further result in the interrupt controller

selecting the processor from the node target processor set in response to determining that a task priority associated with the processor is lower than task priorities associated with the other processors of the node target processor set.

25. The machine-readable medium of claim 22, wherein the plurality of instructions, in response to being executed, further result in the interrupt controller

selecting the processor from the node target processor set based at least upon a task priority associated with the processor.

26. The machine-readable medium of claim 22, wherein the plurality of instructions, in response to being executed, further result in the interrupt controller

applying a first find algorithm to the destination identifier of the interrupt message to identify the default processor for the interrupt, a starting position of the first find algorithm being based at least in part upon the load balancing value of the interrupt message.

27. An interrupt controller comprising

a plurality of storage elements, each storage element associated with an interrupt and storing a destination identifier identifying a target processor set to process the associated interrupt and a vector identifying an interrupt service routine to service the associated interrupt;

an interrupt manager to generate, in response to detecting an interrupt, an interrupt message comprising the destination identifier and the vector associated with the detected interrupt, and a load balancing value to help balance servicing of the detected interrupt among the target processor set identified by the destination identifier; and

a load balancer to update the load balancing value in response to the detected interrupt.

28. The interrupt controller of claim 27, wherein

the load balancer comprises a wrap-around counter that increments the load balancing value in response to each interrupt detected by the interrupt manager.

29. An interrupt controller, comprising

a plurality of storage elements comprising a plurality of identifiers that identify processors of a node processor set associated with the interrupt controller;

and

an interrupt manager

to receive a first interrupt message comprising a load balancing value and a destination identifier that identifies a target processor set to service an interrupt associated with the first interrupt message, and

to provide the node processor set with a second interrupt message comprising an identifier selected from the plurality of storage elements based upon the load balancing value and the destination identifier, the identifier identifying a processor of the node processor set to service the interrupt associated with the first interrupt message.

30. The interrupt controller of claim 29, wherein

the plurality of storage elements further comprise a plurality of priority values identifying priorities associated with processors of the node processor set, and

the interrupt manager selects the identifier based further upon the priority values of the plurality of storage elements that are associated with the target processor set.