Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation

• US 6,813,673 B2
• Filed: 04/30/2001
• Issued: 11/02/2004
• Est. Priority Date: 04/30/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tischler, Brett A., Kotlowski, Kenneth James
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/845,455
• Publication Number:
  US 20020161953A1
• Time in Patent Office: 1,282 Days
• Field of Search: 710/305, 710/316-317, 710/36-45, 710/107-125, 710/240-244
• US Class Current: 710/305
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.

Claims

1. A bus interface unit for transferring data between a plurality of bus devices, said bus interface unit comprising:

1) a first bus device interface comprising;

a) a first incoming request bus for receiving request packets from a first one of said plurality of bus devices;

b) a first outgoing request bus for transmitting request packets to said first bus device;

c) a first incoming data bus for receiving data packets from said first bus device; and

d) a first outgoing data bus for transmitting data packets to said first bus device;

2) a second bus device interface comprising;

a) a second incoming request bus for receiving request packets from a second one of said plurality of bus devices;

b) a second outgoing request bus for transmitting request packets to said second bus device;

c) a second incoming data bus for receiving data packets from said second bus device; and

d) a second outgoing data bus for transmitting data packets to said second bus device;

3) a time slice timer capable of producing a current time slice value; and

4) an arbitration circuit capable of;

a) determining a first priority level associated with a first request packet received from said first bus device and capable of determining a second priority level associated with a second request packet received from said second bus device;

b) determining a fixed time slice range associated with said first bus device; and

c) comparing said fixed time slice range with said current time slice value.

2. The bus interface unit as set forth in claim 1 wherein said arbitration circuit compares said first priority level and said second priority level to determine which of said first and second priority levels is higher.

3. The bus interface unit as set forth in claim 2 wherein said arbitration circuit, in response to a determination that said first priority level is higher that said second priority level, causes said bus interface unit to process said first request packet prior to processing said second request packet.

4. The bus interface unit as set forth in claim 2 wherein said arbitration circuit, in response to a determination that said first priority level is equal to said second priority level and that said current time slice value is not within said fixed time slice range, causes said bus interface unit to process said first and second request packets on a rotating turn basis.

5. The bus interface unit as set forth in claim 1 wherein said arbitration circuit, in response to a determination that said current time slice value is within said fixed time slice range, causes said bus interface unit to process said first request packet prior to processing said second request packet.

6. The bus interface unit as set forth in claim 1 wherein said arbitration circuit, in response to a determination that said current time slice value is within said fixed time slice range, causes said bus interface unit to process said first request packet prior to processing any pending request packet received by said bus interface unit.

7. An integrated circuit data comprising:

1) N bus devices capable of transferring data with one another; and

2) a bus interface unit for transferring data between said N bus devices, said bus interface unit comprising;

a) N bus interfaces, each of said N bus interfaces comprising;

i) an incoming request bus for receiving request packets from one of said N bus devices;

ii) an outgoing request bus for transmitting request packets to said one of said N bus devices;

iii) an incoming data bus for receiving data packets from said one of said N bus devices; and

iv) an outgoing data bus for transmitting data packets to said one of said N bus devices;

b) a time slice timer capable of producing a current time slice value; and

c) an arbitration circuit capable of;

a) determining a first priority level associated with a first request packet received from a first bus device and capable of determining a second priority level associated with a second request packet is received from a second bus device;

b) determining a fixed time slice range associated with said first bus device; and

c) comparing said fixed time slice range with said current time slice value.

8. The integrated circuit as set forth in claim 7 wherein said arbitration circuit compares said first priority level and said second priority level to determine which of said first and second priority levels is higher.

9. The integrated circuit as set forth in claim 8 wherein said arbitration circuit, in response to a determination that said first priority level is higher than said second priority level, causes said bus interface unit to process said first request packet prior to processing said second request packet.

10. The integrated circuit as set forth in claim 8 wherein said arbitration circuit, in response to a determination that said first priority level is equal to said second priority level and that said current time slice value is not within said fixed time slice range, causes said bus interface unit to process said first and second request packets on a rotating turn basis.

11. The integrated circuit as set forth in claim 7 wherein said arbitration circuit, in response to a determination that said current time slice value is within said fixed time slice range, causes said bus interface unit to process said first request packet prior to processing said second request packet.

12. The integrated circuit as set forth in claim 7 wherein said arbitration circuit, in response to a determination that said current time slice value is within said fixed time slice range, causes said bus interface unit to process said first request packet prior to processing any pending request packet received by said bus interface unit.

13. For use in a bus interface unit comprising N bus interfaces, each of the N bus interfaces comprising:

i) an incoming request bus for receiving request packets from a corresponding one of N bus devices;

ii) an outgoing request bus for transmitting request packets to the corresponding bus device;

iii) an incoming data bus for receiving data packets from the corresponding bus device; and

iv) an outgoing data bus for transmitting data packets to the corresponding bus device, a method of arbitrating requests received from the N bus interfaces, the method comprising the steps of;

determining a first priority level associated with a first request packet received from a first bus device;

determining a second priority level associated with a second request packet received from a second bus device;

generating a current time slice value;

comparing the current time slice value with a fixed time slice range associated with the first bus device; and

comparing the first priority level and the second priority level to determine which of the first and second priority levels is higher.

14. The method as set forth in claim 13 further comprising the step, in response to a determination that the first priority level is higher that the second priority level, of processing the first request packet prior to processing the second request packet.

15. The method as set forth in claim 13 further comprising the step, in response to a determination that the first priority level is equal to the second priority level and that said current time slice value is not within said fixed time slice range, of processing the first and second request packets on a rotating turn basis.

16. The method as set forth in claim 13 further comprising the step, in response to a determination that the current time slice value is within the fixed time slice range, of processing the first request packet prior to processing the second request packet.

17. The method as set forth in claim 13 further comprising the step, in response to a determination that the current time slice value is within the fixed time slice range, of processing the first request packet prior to processing any pending request packet received by the bus interface unit.