×

Dual-edge fifo interface

  • US 6,813,674 B1
  • Filed: 05/12/2000
  • Issued: 11/02/2004
  • Est. Priority Date: 06/17/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A dual-edge FIFO interface, comprising:

  • a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full;

    a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full; and

    a register block in communication with the host FIFO and the target FIFO;

    wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×