Dual-edge fifo interface

• US 6,813,674 B1
• Filed: 05/12/2000
• Issued: 11/02/2004
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: St Clair Intellectual Property Consultants Incorporated
• Original Assignee: St Clair Intellectual Property Consultants Incorporated
• Inventors: Velasco, Francisco, Phung, Xuyen N., Mitchell, Phillip M., Fung, Henry T.
• Primary Examiner(s): Jean, Frantz B.
• Application Number:
  US09/570,318
• Time in Patent Office: 1,635 Days
• Field of Search: 710/129, 710/130, 710/52, 710/55, 710/57, 711/131, 711/149
• US Class Current: 710/311
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3259 Power saving in cursor control device, e.g. mouse, joystick, trackball
• CPC Class Codes: G06F 1/3271 Power saving in keyboard
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

Claims

1. A dual-edge FIFO interface, comprising:

a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full;

a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full; and

a register block in communication with the host FIFO and the target FIFO;

wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

2. A dual-edge FIFO interface as in claim 1, wherein the interface is configurable as a synchronous FIFO by removing or bypassing synchronization.

3. A dual-edge FIFO interface as in claim 1, wherein the interface is configurable as an asynchronous FIFO using synchronization signals.

4. A dual edge FIFO interface as in claim 1, wherein the interface is configurable with different combination RAM or block register size.

5. A dual edge FIFO interface as in claim 1, wherein the interface is configurable to receive and/or transmit data at different data rates.

6. A dual edge FIFO interface as in claim 1, wherein the interface is further operative to receive data on both edges of the host clock.